patch-2.4.22 linux-2.4.22/arch/mips/mm/loadmmu.c

• Lines: 133
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/mm/loadmmu.c
• Orig date: 2002-11-28 15:53:10.000000000 -0800

diff -urN linux-2.4.21/arch/mips/mm/loadmmu.c linux-2.4.22/arch/mips/mm/loadmmu.c
@@ -1,7 +1,11 @@
 /*
- * loadmmu.c: Setup cpu/cache specific function ptrs at boot time.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  */
@@ -27,13 +31,13 @@
 void (*___flush_cache_all)(void);
 void (*_flush_cache_mm)(struct mm_struct *mm);
 void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
-			  unsigned long end);
+	unsigned long end);
 void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
-void (*_flush_cache_sigtramp)(unsigned long addr);
 void (*_flush_icache_range)(unsigned long start, unsigned long end);
 void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
 
-void (*_flush_page_to_ram)(struct page * page);
+void (*_flush_cache_sigtramp)(unsigned long addr);
+void (*_flush_data_cache_page)(unsigned long addr);
 void (*_flush_icache_all)(void);
 
 #ifdef CONFIG_NONCOHERENT_IO
@@ -49,49 +53,31 @@
 
 #endif /* CONFIG_NONCOHERENT_IO */
 
-
 extern void ld_mmu_r23000(void);
 extern void ld_mmu_r4xx0(void);
 extern void ld_mmu_tx39(void);
-extern void ld_mmu_tx49(void);
-extern void ld_mmu_r5432(void);
 extern void ld_mmu_r6000(void);
-extern void ld_mmu_rm7k(void);
 extern void ld_mmu_tfp(void);
 extern void ld_mmu_andes(void);
 extern void ld_mmu_sb1(void);
-extern void ld_mmu_mips32(void);
+extern void sb1_tlb_init(void);
 extern void r3k_tlb_init(void);
 extern void r4k_tlb_init(void);
 extern void sb1_tlb_init(void);
 
-void __init loadmmu(void)
+void __init load_mmu(void)
 {
-	if (mips_cpu.options & MIPS_CPU_4KTLB) {
-#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
-    defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
-    defined(CONFIG_CPU_NEVADA)
+	if (cpu_has_4ktlb) {
+#if defined(CONFIG_CPU_R4X00)  || defined(CONFIG_CPU_VR41XX) || \
+    defined(CONFIG_CPU_R4300)  || defined(CONFIG_CPU_R5000)  || \
+    defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432)  || \
+    defined(CONFIG_CPU_R5500)  || defined(CONFIG_CPU_MIPS32) || \
+    defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
+    defined(CONFIG_CPU_RM7000)
 		ld_mmu_r4xx0();
 		r4k_tlb_init();
 #endif
-#if defined(CONFIG_CPU_RM7000)
-		ld_mmu_rm7k();
-		r4k_tlb_init();
-#endif
-#if defined(CONFIG_CPU_R5432) || defined(CONFIG_CPU_R5500)
-		ld_mmu_r5432();
-		r4k_tlb_init();
-#endif
-#if defined(CONFIG_CPU_TX49XX)
-		ld_mmu_tx49();
-		r4k_tlb_init();
-#endif
-
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-		ld_mmu_mips32();
-		r4k_tlb_init();
-#endif
-	} else switch(mips_cpu.cputype) {
+	} else switch (current_cpu_data.cputype) {
 #ifdef CONFIG_CPU_R3000
 	case CPU_R2000:
 	case CPU_R3000:
@@ -100,19 +86,11 @@
 		ld_mmu_r23000();
 		r3k_tlb_init();
 		break;
-	case CPU_TX3912:
-	case CPU_TX3922:
-	case CPU_TX3927:
-	case CPU_TX39XX:
-		ld_mmu_tx39();
-		r3k_tlb_init();
-		break;
 #endif
 #ifdef CONFIG_CPU_TX39XX
 	case CPU_TX3912:
 	case CPU_TX3922:
 	case CPU_TX3927:
-	case CPU_TX39XX:
 		ld_mmu_tx39();
 		r3k_tlb_init();
 		break;
@@ -120,8 +98,8 @@
 #ifdef CONFIG_CPU_R10000
 	case CPU_R10000:
 	case CPU_R12000:
-		ld_mmu_andes();
-		r4k_tlb_init();
+		ld_mmu_r4xx0();
+		andes_tlb_init();
 		break;
 #endif
 #ifdef CONFIG_CPU_SB1
@@ -130,6 +108,11 @@
 		sb1_tlb_init();
 		break;
 #endif
+
+	case CPU_R8000:
+		panic("R8000 is unsupported");
+		break;
+
 	default:
 		panic("Yeee, unsupported mmu/cache architecture.");
 	}