patch-2.2.6 linux/arch/i386/kernel/io_apic.c

• Lines: 148
• Date: Thu Apr 15 08:59:42 1999
• Orig file: v2.2.5/linux/arch/i386/kernel/io_apic.c
• Orig date: Tue Feb 23 15:21:32 1999

diff -u --recursive --new-file v2.2.5/linux/arch/i386/kernel/io_apic.c linux/arch/i386/kernel/io_apic.c
@@ -293,7 +293,8 @@
 	for (i = 0; i < mp_irq_entries; i++) {
 		int lbus = mp_irqs[i].mpc_srcbus;
 
-		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA) &&
+		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
+		     mp_bus_id_to_type[lbus] == MP_BUS_EISA) &&
 		    (mp_irqs[i].mpc_irqtype == type) &&
 		    (mp_irqs[i].mpc_srcbusirq == 0x00))
 
@@ -326,20 +327,7 @@
 }
 
 /*
- * Unclear documentation on what a "conforming ISA interrupt" means.
- *
- * Should we, or should we not, take the ELCR register into account?
- * It's part of the EISA specification, but maybe it should only be
- * used if the interrupt is actually marked as EISA?
- *
- * Oh, well. Don't do it until somebody tells us what the right thing
- * to do is..
- */
-#undef USE_ELCR_TRIGGER_LEVEL
-#ifdef USE_ELCR_TRIGGER_LEVEL
-
-/*
- * ISA Edge/Level control register, ELCR
+ * EISA Edge/Level control register, ELCR
  */
 static int __init EISA_ELCR(unsigned int irq)
 {
@@ -349,18 +337,22 @@
 	}
 	printk("Broken MPtable reports ISA irq %d\n", irq);
 	return 0;
-}	
+}
 
-#define default_ISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].mpc_dstirq))
-#define default_ISA_polarity(idx)	(0)
+/* EISA interrupts are always polarity zero and can be edge or level
+ * trigger depending on the ELCR value.  If an interrupt is listed as
+ * EISA conforming in the MP table, that means its trigger type must
+ * be read in from the ELCR */
 
-#else
+#define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].mpc_dstirq))
+#define default_EISA_polarity(idx)	(0)
+
+/* ISA interrupts are always polarity zero edge triggered, even when
+ * listed as conforming in the MP table. */
 
 #define default_ISA_trigger(idx)	(0)
 #define default_ISA_polarity(idx)	(0)
 
-#endif
-
 static int __init MPBIOS_polarity(int idx)
 {
 	int bus = mp_irqs[idx].mpc_srcbus;
@@ -380,6 +372,11 @@
 					polarity = default_ISA_polarity(idx);
 					break;
 				}
+				case MP_BUS_EISA:
+				{
+					polarity = default_EISA_polarity(idx);
+					break;
+				}
 				case MP_BUS_PCI: /* PCI pin */
 				{
 					polarity = 1;
@@ -439,6 +436,11 @@
 					trigger = default_ISA_trigger(idx);
 					break;
 				}
+				case MP_BUS_EISA:
+				{
+					trigger = default_EISA_trigger(idx);
+					break;
+				}
 				case MP_BUS_PCI: /* PCI pin, level */
 				{
 					trigger = 1;
@@ -503,6 +505,7 @@
 	switch (mp_bus_id_to_type[bus])
 	{
 		case MP_BUS_ISA: /* ISA pin */
+		case MP_BUS_EISA:
 		{
 			irq = mp_irqs[idx].mpc_srcbusirq;
 			break;
@@ -910,6 +913,8 @@
 static void __init construct_default_ISA_mptable(void)
 {
 	int i, pos = 0;
+	const int bus_type = (mpc_default_type == 2 || mpc_default_type == 3 ||
+			      mpc_default_type == 6) ? MP_BUS_EISA : MP_BUS_ISA;
 
 	for (i = 0; i < 16; i++) {
 		if (!IO_APIC_IRQ(i))
@@ -917,14 +922,14 @@
 
 		mp_irqs[pos].mpc_irqtype = mp_INT;
 		mp_irqs[pos].mpc_irqflag = 0;		/* default */
-		mp_irqs[pos].mpc_srcbus = MP_BUS_ISA;
+		mp_irqs[pos].mpc_srcbus = 0;
 		mp_irqs[pos].mpc_srcbusirq = i;
 		mp_irqs[pos].mpc_dstapic = 0;
 		mp_irqs[pos].mpc_dstirq = i;
 		pos++;
 	}
 	mp_irq_entries = pos;
-	mp_bus_id_to_type[0] = MP_BUS_ISA;
+	mp_bus_id_to_type[0] = bus_type;
 
 	/*
 	 * MP specification 1.4 defines some extra rules for default
@@ -1178,13 +1183,23 @@
 			 */
 			if (i < 16)
 				disable_8259A_irq(i);
-		} else
+		} else {
+			if (!IO_APIC_IRQ(i))
+				continue;
+
 			/*
-			 * we have no business changing low ISA
-			 * IRQs.
+			 * Hmm.. We don't have an entry for this,
+			 * so default to an old-fashioned 8259
+			 * interrupt if we can..
 			 */
-			if (IO_APIC_IRQ(i))
-				irq_desc[i].handler = &no_irq_type;
+			if (i < 16) {
+				make_8259A_irq(i);
+				continue;
+			}
+
+			/* Strange. Oh, well.. */
+			irq_desc[i].handler = &no_irq_type;
+		}
 	}
 	init_IRQ_SMP();
 }