patch-2.2.4 linux/arch/sparc64/kernel/dtlb_backend.S

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diff -u --recursive --new-file v2.2.3/linux/arch/sparc64/kernel/dtlb_backend.S linux/arch/sparc64/kernel/dtlb_backend.S
@@ -1,4 +1,4 @@
-/* $Id: dtlb_backend.S,v 1.6 1998/09/24 03:21:32 davem Exp $
+/* $Id: dtlb_backend.S,v 1.7 1998/12/16 04:33:28 davem Exp $
  * dtlb_backend.S: Back end to DTLB miss replacement strategy.
  *                 This is included directly into the trap table.
  *
@@ -37,28 +37,30 @@
 	be,pn		%xcc, sparc64_vpte_nucleus	! Is it from Nucleus?
 	 and		%g1, 0xffe, %g1			! Mask PMD offset bits
 	brnz,pt		%g5, sparc64_vpte_continue	! Yep, go like smoke
-	 nop						! Pipe bubble...
+	 add		%g1, %g1, %g1			! Position PMD offset some more
 	srlx		%g6, (PGD_SHIFT - 2), %g5	! Position PGD offset
 	and		%g5, 0xffc, %g5			! Mask PGD offset
 
 /* TLB1 ** ICACHE line 3: Quick VPTE miss	  	*/
 	lduwa		[%g7 + %g5] ASI_PHYS_USE_EC, %g5! Load PGD
-	brz,pn		%g5, 2f				! Valid?
+	brz,pn		%g5, vpte_noent			! Valid?
+sparc64_kpte_continue:
+	 sllx		%g5, 11, %g5			! Shift into place
 sparc64_vpte_continue:
-	 add		%g1, %g1, %g1			! Position PMD offset once again
 	lduwa		[%g5 + %g1] ASI_PHYS_USE_EC, %g5! Load PMD
-	brz,pn		%g5, 2f				! Valid?
+	sllx		%g5, 11, %g5			! Shift into place
+	brz,pn		%g5, vpte_noent			! Valid?
 	 sllx		%g2, 62, %g1			! Put _PAGE_VALID into %g1
 	or		%g5, VPTE_BITS, %g5		! Prepare VPTE data
-	or		%g5, %g1, %g5			! ...
 
 /* TLB1 ** ICACHE line 4: Quick VPTE miss	  	*/
+	or		%g5, %g1, %g5			! ...
 	mov		TLB_SFSR, %g1			! Restore %g1 value
 	stxa		%g5, [%g0] ASI_DTLB_DATA_IN	! Load VPTE into TLB
-	membar		#Sync				! Synchronize ASI stores
 	stxa		%g4, [%g1 + %g1] ASI_DMMU	! Restore previous TAG_ACCESS
 	retry						! Load PTE once again
-2:	mov		TLB_SFSR, %g1			! Restore %g1 value
+vpte_noent:
+	mov		TLB_SFSR, %g1			! Restore %g1 value
 	stxa		%g4, [%g1 + %g1] ASI_DMMU	! Restore previous TAG_ACCESS
 	done						! Slick trick
 

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