patch-2.2.18 linux/include/asm-arm/proc-armv/assembler.h

• Lines: 121
• Date: Fri Sep 15 23:32:34 2000
• Orig file: v2.2.17/include/asm-arm/proc-armv/assembler.h
• Orig date: Fri Apr 21 12:46:49 2000

diff -u --new-file --recursive --exclude-from /usr/src/exclude v2.2.17/include/asm-arm/proc-armv/assembler.h linux/include/asm-arm/proc-armv/assembler.h
@@ -6,79 +6,81 @@
  * This file contains arm architecture specific defines
  * for the different processors
  */
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
 
-/*
- * LOADREGS: multiple register load (ldm) with pc in register list
- *		(takes account of ARM6 not using ^)
- *
- * RETINSTR: return instruction: adds the 's' in at the end of the
- *		instruction if this is not an ARM6
- *
- * SAVEIRQS: save IRQ state (not required on ARM2/ARM3 - done
- *		implicitly
- *
- * RESTOREIRQS: restore IRQ state (not required on ARM2/ARM3 - done
- *		implicitly with ldm ... ^ or movs.
- *
- * These next two need thinking about - can't easily use stack... (see system.S)
- * DISABLEIRQS: disable IRQS in SVC mode
- *
- * ENABLEIRQS: enable IRQS in SVC mode
- *
- * USERMODE: switch to USER mode
- *
- * SVCMODE: switch to SVC mode
- */
-
-#define N_BIT	(1 << 31)
-#define Z_BIT	(1 << 30)
-#define C_BIT	(1 << 29)
-#define V_BIT	(1 << 28)
-
-#define PCMASK	0
-
-#ifdef __ASSEMBLER__
-
-#define I_BIT	(1 << 7)
-#define F_BIT	(1 << 6)
-
-#define MODE_FIQ26	0x01
-#define MODE_FIQ32	0x11
+#define MODE_USR	USR_MODE
+#define MODE_FIQ	FIQ_MODE
+#define MODE_IRQ	IRQ_MODE
+#define MODE_SVC	SVC_MODE
 
-#define DEFAULT_FIQ	MODE_FIQ32
+#define DEFAULT_FIQ	MODE_FIQ
 
+/*
+ * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
+ * RETINSTR - return instruction (eg, mov pc, lr)
+ */
+#ifdef __STDC__
 #define LOADREGS(cond, base, reglist...)\
 	ldm##cond	base,reglist
 
 #define RETINSTR(instr, regs...)\
 	instr	regs
+#else
+#define LOADREGS(cond, base, reglist...)\
+	ldm/**/cond	base,reglist
 
+#define RETINSTR(instr, regs...)\
+	instr		regs
+#endif
+
+/*
+ * No nop required after mode change
+ */
 #define MODENOP
 
+/*
+ * Change to `mode'
+ */
 #define MODE(savereg,tmpreg,mode) \
 	mrs	savereg, cpsr; \
 	bic	tmpreg, savereg, $0x1f; \
 	orr	tmpreg, tmpreg, $mode; \
 	msr	cpsr, tmpreg
 
+/*
+ * Restore mode
+ */
 #define RESTOREMODE(savereg) \
 	msr	cpsr, savereg
 	
+/*
+ * save interrupt state (uses stack)
+ */
 #define SAVEIRQS(tmpreg)\
 	mrs	tmpreg, cpsr; \
 	str	tmpreg, [sp, $-4]!
 
+/*
+ * restore interrupt state (uses stack)
+ */
 #define RESTOREIRQS(tmpreg)\
 	ldr	tmpreg, [sp], $4; \
 	msr	cpsr, tmpreg
 
+/*
+ * disable IRQs
+ */
 #define DISABLEIRQS(tmpreg)\
 	mrs	tmpreg , cpsr; \
 	orr	tmpreg , tmpreg , $I_BIT; \
 	msr	cpsr, tmpreg
 
+/*
+ * enable IRQs
+ */
 #define ENABLEIRQS(tmpreg)\
 	mrs	tmpreg , cpsr; \
 	bic	tmpreg , tmpreg , $I_BIT; \
 	msr	cpsr, tmpreg
-#endif