patch-2.2.18 linux/arch/i386/kernel/mtrr.c

• Lines: 137
• Date: Wed Sep 27 21:05:41 2000
• Orig file: v2.2.17/arch/i386/kernel/mtrr.c
• Orig date: Fri Apr 21 12:45:45 2000

diff -u --new-file --recursive --exclude-from /usr/src/exclude v2.2.17/arch/i386/kernel/mtrr.c linux/arch/i386/kernel/mtrr.c
@@ -305,7 +305,7 @@
 static unsigned int ascii_buf_bytes = 0;
 #endif
 static unsigned int *usage_table = NULL;
-static spinlock_t main_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t main_lock  __attribute((unused)) = SPIN_LOCK_UNLOCKED;
 
 /*  Private functions  */
 #ifdef CONFIG_PROC_FS
@@ -337,7 +337,8 @@
 	if (boot_cpu_data.x86 >= 6) break; /* Athlon and post-Athlon CPUs */
 	/* else fall through */
       case X86_VENDOR_CENTAUR:
-	return;
+	if(boot_cpu_data.x86 != 6)
+		return;
 	/*break;*/
     }
     /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
@@ -361,6 +362,7 @@
     {
       case X86_VENDOR_AMD:
       case X86_VENDOR_INTEL:
+      case X86_VENDOR_CENTAUR:
 	/*  Disable MTRRs, and set the default type to uncached  */
 	rdmsr (MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
 	wrmsr (MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL, ctxt->deftype_hi);
@@ -384,8 +386,11 @@
 	if (boot_cpu_data.x86 >= 6) break; /* Athlon and post-Athlon CPUs */
 	/* else fall through */
       case X86_VENDOR_CENTAUR:
-	__restore_flags (ctxt->flags);
-	return;
+	if(boot_cpu_data.x86 != 6)
+	{
+		__restore_flags (ctxt->flags);
+		return;
+	}
 	/*break;*/
     }
     /*  Flush caches and TLBs  */
@@ -396,6 +401,7 @@
     {
       case X86_VENDOR_AMD:
       case X86_VENDOR_INTEL:
+      case X86_VENDOR_CENTAUR:
 	wrmsr (MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
 	break;
       case X86_VENDOR_CYRIX:
@@ -434,9 +440,17 @@
 	/*break;*/
       case X86_VENDOR_CYRIX:
 	/*  Cyrix have 8 ARRs  */
+	return 8;
       case X86_VENDOR_CENTAUR:
         /*  and Centaur has 8 MCR's  */
-	return 8;
+	if(boot_cpu_data.x86==5)
+		return 8;
+	/*  the cyrix III has intel compatible MTRR */
+	if(boot_cpu_data.x86==6)
+	{
+		rdmsr (MTRRcap_MSR, config, dummy);
+		return (config & 0xff);
+	}
 	/*break;*/
     }
     return 0;
@@ -452,12 +466,15 @@
       case X86_VENDOR_AMD:
 	if (boot_cpu_data.x86 < 6) return 1; /* pre-Athlon CPUs */
 	/* else fall through */
+      case X86_VENDOR_CENTAUR:
+        if (boot_cpu_data.x86 == 5)
+        	return 1;	/* C6 */
+        /* CyrixIII is Intel like */
       case X86_VENDOR_INTEL:
 	rdmsr (MTRRcap_MSR, config, dummy);
 	return (config & (1<<10));
 	/*break;*/
       case X86_VENDOR_CYRIX:
-      case X86_VENDOR_CENTAUR:
 	return 1;
 	/*break;*/
     }
@@ -1135,7 +1152,7 @@
 	    printk ("mtrr: size: %lx  base: %lx\n", size, base);
 	    return -EINVAL;
 	}
-        if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR)
+        if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 5)
 	{
 	    if (centaur_ctx->type_bits[type]==0) {
 		printk ("mtrr: type not supported\n");
@@ -1758,8 +1775,16 @@
 	get_free_region = cyrix_get_free_region;
 	break;
      case X86_VENDOR_CENTAUR:
-        get_mtrr = centaur_get_mcr;
-        set_mtrr_up = centaur_set_mcr_up;
+        if(boot_cpu_data.x86 == 5)
+        {
+        	get_mtrr = centaur_get_mcr;
+	        set_mtrr_up = centaur_set_mcr_up;
+	}
+	if(boot_cpu_data.x86 == 6)
+	{
+		get_mtrr = intel_get_mtrr;
+		set_mtrr_up = intel_set_mtrr_up;
+	}
         break;
     }
 }   /*  End Function mtrr_setup  */
@@ -1783,8 +1808,11 @@
       case X86_VENDOR_CYRIX:
 	cyrix_arr_init ();
 	break;
-      case X86_VENDOR_CENTAUR:
-        centaur_mcr_init ();
+      case X86_VENDOR_CENTAUR:		/* C6 and Cyrix III have different ones */
+      	if(boot_cpu_data.x86 == 5)
+	        centaur_mcr_init ();
+	if(boot_cpu_data.x86 == 6)
+		get_mtrr_state(&smp_mtrr_state);
         break;
     }
 }   /*  End Function mtrr_init_boot_cpu  */
@@ -1856,7 +1884,8 @@
 	cyrix_arr_init ();
 	break;
       case X86_VENDOR_CENTAUR:
-        centaur_mcr_init ();
+        if(boot_cpu_data.x86 == 5)
+        	centaur_mcr_init ();
         break;
     }
 #  endif  /*  !__SMP__  */