A HARDWARE-FRIENDLY ENCRYPTION SCHEME - HARDWARE ISSUES

Please refer to the file basics.txt to get a general outline of the scheme,
or sm.c for a sample C program that illustrates the idea.

The reason for wanting to implement something in hardware is that it would
want to be used in cellular phones and faxes, and the data rates are
therefore fixed and reasonably fast (as compared to email or other text
messages). The hope is that with cheap dedicated hardware, it will be
possible to implement a really secure scheme without compromising encryption
speed.

I haven't done a real Xilinx design of this yet. I hazard a guess that it
will fit in an XC3042, which is a $25 or $30 part, and will operate well
into the tens of megabytes per second. It may be primarily limited by the
key memory. Offhand I don't know what volume pricing is like on Xilinx parts
these days, but distributors know all that stuff.

I am interested in coming up with a configuration for this circuit that will
be as easy to use as possible for equipment manufacturers. In order to do
that, I am looking for any information anyone can provide about typical fax
and cellular phone designs, particularly:

(1) In faxes and cellular phones, is the data routed thru the processor, or
does it go thru a special data path that never goes near the processor? This
would determine whether the chip should expect to sit on a single tristate
bus, or have separate input and output buses, and would affect how data is
clocked into and out of the chip.

(2) Are the timing requirements of fax/phone circuits sufficiently lax that
the chip could steal cycles to read from the micro's EPROM? Otherwise it
would require its own EPROM, and some extra internal logic.

Please address any questions or comments to <wware@world.std.com>.

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