SHELL    = /bin/sh

ASIMUT   = $(TOP)/bin/asimut
DESB     = $(TOP)/bin/desb
DRUC     = $(TOP)/bin/druc
GENLIB   = $(TOP)/bin/genlib
LVX      = $(TOP)/bin/lvx
LYNX     = $(TOP)/bin/lynx
PROOF    = $(TOP)/bin/proof
RING     = $(TOP)/bin/ring
S2R      = $(TOP)/bin/s2r
SCR      = $(TOP)/bin/scr

#################################################################
#   S2R is the final step of the conception, it generates the   # 
#   real layout description using the desired technology        #
#################################################################

all : amd2901.cif

amd2901.cif : proof_end
	MBK_IN_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	RDS_TECHNO_NAME=$(TOP)/etc/prol12.rds ;\
	RDS_IN=cif ;\
	RDS_OUT=cif ;\
	export MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB RDS_TECHNO_NAME RDS_IN RDS_OUT;\
	$(S2R) -c chip amd2901

#################################################################
# PROOF between amd.vbe chip.vbe				#
#################################################################

proof_end : chip.vbe 
	MBK_WORK_LIB=. ;\
	export MBK_WORK_LIB;\
	$(PROOF) -a -d amd chip ;\
	echo "proof_end done" >> proof_end

#################################################################
# DESB on the chip						#
#################################################################

chip.vbe : asimut_end
	MBK_IN_LO=al ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
	$(DESB) chip -i -v

#################################################################
# asimut of the chip						#
#################################################################

asimut_end : lvx_chip
	MBK_IN_LO=al ;\
	VH_PATSFX=pat ;\
	VH_MAXERR=10 ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_IN_LO VH_PATSFX VH_MAXERR MBK_WORK_LIB MBK_CATA_LIB;\
	$(ASIMUT) chip pattern res_pattern
	echo " asimut_end done " >> asimut_end

#################################################################
#   LVX of the chip                                             #
#################################################################

lvx_chip : chip.al
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_WORK_LIB MBK_CATA_LIB;\
	$(LVX) vst al chip chip
	echo " lvx_chip done" >> lvx_chip

#################################################################
#   LYNX of the chip                                            #
#################################################################

chip.al : druc_chip
	MBK_OUT_LO=al ;\
	MBK_IN_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_OUT_LO MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB;\
	$(LYNX) chip 

#################################################################
#   DRUC is a design rules checker, it looks for design         #
#   in the layout description "chip.ap"                         #
#################################################################

druc_chip : chip.ap 
	MBK_IN_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB;\
	$(DRUC) chip ;\
	echo "druc_chip done " >> druc_chip


#################################################################
#   RING routes the connections between the pads and the heart. #
#################################################################

chip.ap : lvx_heart chip.rin
	MBK_IN_LO=vst ;\
	MBK_IN_PH=ap ;\
	MBK_OUT_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_IN_LO MBK_IN_PH MBK_OUT_PH MBK_WORK_LIB MBK_CATA_LIB;\
	$(RING) chip chip 

#################################################################
#   LVX of the heart                                            #
#################################################################

lvx_heart : heart.al
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_WORK_LIB MBK_CATA_LIB;\
	$(LVX) vst al heart heart -f
	echo "lvx_heart done " >> lvx_heart

#################################################################
#   LYNX of the heart                                           #
#################################################################

heart.al : druc_heart
	MBK_OUT_LO=al ;\
	MBK_IN_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_OUT_LO MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB;\
	$(LYNX) heart 

#################################################################
#   DRUC is a design rules checker, it looks for design         #
#   in the layout description "heart.ap"                        #
#################################################################

druc_heart : heart.ap
	MBK_IN_PH=ap ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_CATA_LIB MBK_WORK_LIB MBK_IN_PH;\
	$(DRUC) heart ;\
	echo "druc_heart done " >> druc_heart

#################################################################
#   SCR is a standard cells router, it makes an automatic       #
#   placement and routing of the "heart.al" and gives the       #
#   corresponding layout description "heart.ap".                #
#################################################################

heart.ap : asimut_vst
	MBK_IN_PH=ap ;\
	MBK_OUT_PH=ap ;\
	MBK_IN_LO=vst ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
	$(SCR) -p -r heart

#################################################################
#   ASIMUT                                                      #
#   This time the "chip.vst" is                                 #
#   simulated by ASIMUT, using the test patternss "pattern.pat" #
#   previously generated in the behaviour step.                 #
#################################################################

asimut_vst : chip.vst
	MBK_IN_LO=vst ;\
	VH_PATSFX=pat ;\
	VH_MAXERR=10 ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_IN_LO VH_PATSFX VH_MAXERR MBK_WORK_LIB MBK_CATA_LIB;\
	$(ASIMUT) chip pattern result_str ;\
	echo "asimut_vst done " >> asimut_vst

#################################################################
#   GENLIB is a procedural design language upon C.              #
#   every netlist source files with a ".c" extension are compiled
#   by GENLIB which gives the corresponding gate netlists ended #
#   by ".vst" extension                                         #
#################################################################

chip.vst : asimut_vbe chip.c
	(MBK_IN_LO=vst ;\
	MBK_OUT_LO=vst ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12 ;\
	export MBK_IN_LO MBK_OUT_LO MBK_WORK_LIB MBK_CATA_LIB;\
	$(GENLIB) -v chip)

#################################################################
#   ASIMUT                                                      #
#   the  hardware behaviour description "amd.vbe" is            #
#   simulated by ASIMUT, using the test patterns                #
#   previously generated in "pattern.pat".                      #
#################################################################


asimut_vbe : asimut_first
	VH_MAXERR=10 ;\
 	VH_PATSFX=pat ;\
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=.:$(TOP)/cells/scr:$(TOP)/cells/ring/pad12;\
	export VH_MAXERR VH_PATSFX MBK_WORK_LIB MBK_CATA_LIB;\
	$(ASIMUT) -b amd pattern result_beh;\
	echo "asimut_vbe done " >> asimut_vbe

#################################################################
#  Asimut compilation						#
#################################################################

asimut_first : amd.vbe
	MBK_WORK_LIB=. ;\
	MBK_CATA_LIB=. ; \
	export MBK_WORK_LIB MBK_CATA_LIB;\
	$(ASIMUT) -b -c amd;\
	echo "asimut_first done " >> asimut_first

clean :
	-/bin/rm -f *.vst r*.pat *.al *.ap *.grr *.err \
	 	*.o asimut_* druc_* lvx_* proof_* \
	 	*.lis *.cif chip.vbe chip.d* *.SHP \
		*.drc
