Design methodology
------------------

You are now ready to actually design the chip and use the ALLIANCE tools.

The design methodology you are to use is composed of 5 main steps:
1) Behavioral capture and simulation.
2) Netlist capture and validation.
3) physical layout.
4) design validation.
5) symbolic to real conversion.

As you will see, points 2) and 3) must be performed for each level of
hierarchy. Design hierarchy in this example is quite simple, because
we distinguish only two levels: the core level and the chip 
level.

The picture below describes the chip hierarchy.


                      ----------
                      |  chip  |
                      ----------
                           |
                           |
            --------------------------------
            |              |               |
            |              |               |
       -----------    -----------      ----------
       |  core   |    |   pads  | ...  |  pads  |
       -----------    -----------      ----------
         |  |  |
     -----  |  -----              
     |      |      |                

     Standard Cells
 
Press <return> to continue.
