Behavioral capture and simulation
---------------------------------

When designing a chip, the first thing to do is to write its
behavior, based on its functional specifications. In our
example addaccu, we have to modelize an adder, a register, a multiplexer.
We also have to specify in the resulting behavior file that the adder may
take as an input A the result of a previous calculation or a new
input pattern.

Modern behavioral descriptions are written in VHDL.
You should now shift to another shell window and
edit the behavioral description of addaccu by issuing
the following command:
 
> vi addaccu.vbe
 
NB: > stands for csh prompt. It may differ in your environment. You may
also wish to use another text editor. Feel free to do it, as long
as you do not modify the original file.
 
The addaccu.vbe file contains the behavioral description of the circuit.
vbe stands for VHDL behavioral description.
Although this tutorial does no intend to explain the arcanes of
VHDL programming, it's worth noting some interesting points:
 
1) notice that the entity name, addaccu, identifies the circuit.
 
2) examine the circuit interface. You can recognize the
terminals of the previous picture, plus 4 special terminals, known
as supply terminals. The supply terminals are needed for the last
stage of the design, as the original behavioral description
must be matched with an "extracted" behavior.
If this does not make immediate sense to you, do not panic,
everything will be clear in a moment.
 
3) take a look to the functional architecture of addaccu. When
examining it, pay attention to the reg_bit register names of the
accumulator reg0 to reg3, as they will be used later in the
validation stage.
 
4) read carefully the functional description. With a little
work, you can recognize the description of the multiplexer,
the equations of the adder, and the accumulator. It is very
important to notice that the functional description of the circuit
assumes that edge-triggered latches are used.
 
Once you have carefully examined this file, close it and get
back to the shell prompt, for the VHDL compilation stage.

Press <return> to continue.
