*************************************************************************
*       ALLIANCE VLSI/CAD SYSTEM     RELEASE 2.0   14/02/94             *
*************************************************************************

This README file is structured like a FAQ (Frequently Asked Questions)
You should read it entirely before proceeding to the installation of
the whole set of programs. This file contains the basic pointers to
the different documents or manuals found in this release.

Question  1: What is ALLIANCE ?
Question  2: What is ALLIANCE general copyright policy ?
Question  3: How to install ALLIANCE ?
Question  4: How to get started ?
Question  5: What are the differences with the previous release 1.2 ?
Question  6: What is the supported VHDL subset ?
Question  7: What is the available online documentation ?
Question  8: Where are defined the symbolic layout rules ?
Question  9: How is performed the mapping to a target process ?
Question 10: How can I get a complete paper documentation ?
Question 11: What are the supported file formats ?
Question 12: How can I get in touch with the ALLIANCE team ?


Question 1: What is ALLIANCE ?
------------------------------

You can read a general description of the ALLIANCE tools and libraries
by printing the PostScript files OVERVIEW.ps and LIBRARIES.ps located
in the root directory:

> lpr OVERVIEW.ps
> lpr LIBRARIES.ps

Question 2: What is ALLIANCE general copyright policy ?
-------------------------------------------------------

The CAO-VLSI team at MASI follows the general copyright policy defined
by the Free Software Foundation. You can read the ALLIANCE general public
license by issuing:

> more ALLIANCE.COPYING

Question 3: How to install ALLIANCE ?
-------------------------------------

For those architectures supported by ALLIANCE (i.e. SparcStation,
DecSystem 5100, 386 Pc under Linux) first, check the correctness of paths
and Unix development tools in the corresponding file (respectively sparc.mk,
dec.mk and pc.mk) in etc/ directory. Modify the file if necessary. Then,
modify the INSTALL file to choose those ALLIANCE tools you want to be
installed and run the INSTALL file at prompt levwl.

For other architectures your have to create you own `.mk` file in etc/
directiry (take sparc.mk as model).

Binaries are also available for architectures supported by ALLIANCE.

+--------------------------------+
| Distributions          | Size  |
|------------------------+-------|
| Source                 | 40 MB |
| Sparc (SunOS 4.1.1)    | 50 MB |
| DS 5100 (Ultrix 4.3)   | 60 MB |
| 386-PC (linux 0.99.14) | 55 MB |
+--------------------------------+

Question 4: How to get started ?
--------------------------------

You can find three separate tutorials in the tutorials directory:
(see the README file in this directory)

1/ ADDACCU
The design of a very simple chip (adder/accumulator) to get started
with the ALLIANCE tools.

>cd tutorials/addaccu

2/ AMD2901
The design of the 4 bits AMD2901 processor, from the VHDL specification to
the CIF layout, using the ALLIANCE portable standard cells library.

>cd tutorials/amd2901

3/ DLXM
The design of the 32 bits DLX microprocessor (PATTERSON & HENNESSY)
from the VHDL specification to the CIF layout, using the ALLIANCE
data-path compiler and logic synthesis tools.

>cd tutorials/dlxm

Question 5: What are the differences with the previous release 1.2 ?
--------------------------------------------------------------------

The new features of release 2.0 are described in the ALLIANCE.HISTORY
file:

> more ALLIANCE.HISTORY

Question 6: What is the supported VHDL subset ?
-----------------------------------------------

You can find a general presentation of the VHDL subset by issuing the
following commands:

> man vhdl

This gives you an hint about the supported VHDL subset.
There is actually three separate architectures types: "Structural",
"Data-flow", and "Finite-State-Machine"

> man vst

This gives you the VHDL subset supported for structural descriptions.

> man vbe

This gives you the data-flow behavioral subset supported by the simulator
ASIMUT, the logic synthesis tool LOGIC and the formal prover PROOF.

> man fsm

This gives you the VHDL subset used for Finite-State-Machine description
and supported by the FSM synthesis tool SYF.

Question 7: What is the available online documentation ?
--------------------------------------------------------

1) tools
--------

> man asimut            /* VHDL simulator */
> man genpat            /* pattern description */
> man genlib            /* netlist capture and procedural layout */
> man fpgen             /* data-path compiler */
> man dpr               /* data-path router */
> man scr               /* standard cell router */
> man bbr               /* channel router */
> man ring              /* core to pads router */
> man s2r               /* symbolic to real converter */
> man druc              /* design rule checker */
> man lynx              /* netlist extractor */
> man lvx               /* netlist comparator */
> man desb              /* functional abstractor */
> man proof             /* formal prover */
> man syf               /* finite-state-machine synthesizer */
> man logic             /* logic synthesis */
> man netoptim          /* net-list optimiser */
> man genview           /* procedural layout debugger */
> man graal             /* symbolic layout editor */
> man l2p               /* post-script driver */

2) cell libraries
-----------------

> man sclib              /* standard cells library */
> man dplib              /* data-path cells library */
> man padlib             /* pad library */
> man rsa                /* fast adder generator */
> man bsg                /* barrel shifter generator */
> man amg                /* multiplier generator */
> man rfg                /* register file generator */
> man grog               /* high speed ROM generator */
> man rage               /* static RAM generator */

3) ALLIANCE file formats
------------------------

> man vhdl               /* VHDL overview */
> man vst                /* VHDL subset for net-list */
> man vbe                /* VHDL subset for data-flow */
> man fsm                /* VHDL subset for finite-state-machine */
> man al                 /* internal ALLIANCE netlist */
> man ap                 /* internal ALLIANCE symbolic layout */
> man pat                /* internal ALLIANCE pattern description */

4) miscellaneous
----------------

> man catal              /* use of the catalog file */
> man envir              /* about environment variables */
> man prol               /* technology file */


Question 8:  Where are defined the symbolic layout rules ?
-----------------------------------------------------

The symbolic layout rules are specified in the Design Rule Checker
documentation:

> man druc

Question 9:  How is performed the mapping to a target process ?
---------------------------------------------------------------

The actual conversion is performed by the s2r tool:

> man s2r

If you want to parameterize the S2R tool to a new target technology,
you must write a technology file. The method is described in the
postscript file MAPPING.ps

> lpr doc/s2r/MAPPING.ps

Question 10: How can I get a complete paper documentation ?
-----------------------------------------------------------

You will get a print of all manuals of the ALLIANCE tools by issuing
the following commands:

> cd doc
> PRINT_TOOLS_DOC lw

(where 'lw' is the name of your printer)

You can print the detailed standard cells documentation by issuing the
following commands:

> cd doc
> PRINT_CELLS_DOC lw

Question 11: What are the supported file formats ?
--------------------------------------------------

ALLIANCE tools are interfaced to generic data-structures that
support various standard file formats, thanks to a set of
specialized parsers/drivers.
UNIX environment variables are used to select one particular file format.
For a given entity, the file format is defined by the file extension.

1/ symbolic layout view

ALLIANCE          .ap       INPUT   OUTPUT
COMPASS           .cp       INPUT   OUTPUT

2/ physical layout view

CIF               .cif              OUTPUT
GDSII             .gds              OUTPUT

3/ netlist view

ALLIANCE          .al       INPUT   OUTPUT
SPICE             .spi      INPUT   OUTPUT
EDIF 2.0          .edi      INPUT   OUTPUT
VHDL              .vst      INPUT   OUTPUT
COMPASS           .hns      INPUT   OUTPUT
HILO              .cct              OUTPUT

4/ behavioural view

VHDL (data-flow)  .vbe      INPUT   OUTPUT
VHDL (FSM)        .fsm      INPUT

Question 12: How can I get in touch with the ALLIANCE team ?
------------------------------------------------------------

Please use the following mail adresses: `cao-vlsi@masi.ibp.fr'
This will reach all the team that has built Alliance.

If you like to reach all the interested users of Alliance, use:
       alliance@masi.ibp.fr
BE CAREFUL ! This will reach all the users of Alliance through the world.
You can subscribe or unsubscribe to this mailing-list of registered users
of Alliance in the world by sending a mail to
       alliance-request@masi.ibp.fr

You may get ALLIANCE by two distinct means:
       1) by anonymous FTP
       2) by sending a blank tape (we can write DC 600A 60 MBytes,
          DC 6150 150 MBytes and ExaByte 8mm 2,3 GBytes) with your
          complete affiliation to the following address:

          Laboratoire MASI/CAO-VLSI
          Tour 55-65, 2eme etage, Porte 13
          Universite Pierre et Marie Curie (PARIS VI)
          4, place Jussieu 75252 PARIS Cedex 05
          FRANCE

          Fax                : 33 1 44 27 62 86
          support e-mail     : cao-vlsi@masi.ibp.fr
          Users Mailing-list : alliance@masi.ibp.fr
          ftp site           : cao-vlsi.ibp.fr
