DESB(1)

NAME

desb
    - Functional abstraction of CMOS circuits

ORIGIN
This software belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
Fax: (33-1) 44.27.62.86 ; E-mail cao-vlsi@masi.ibp.fr

SYNOPSIS
desb file1 [file2] [-h] [-p=n] [-v] [-i]

DESCRIPTION
DESB is a functional abstractor for CMOS digital circuits. It provides a VHDL data flow description from a transistor level description of the circuit. The transistor net-list can be flat or hierarchical. The subset of VHDL used by DESB is supported by ASIMUT, LOGIC and PROOF.
Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers are expressed as VHDL Register signal. Desb does not use a predefined gate library except for latchs and flip-flops. All styles or circuitry are supported: dual-cmos, precharge, pass-transistor...
All power supplies and grounds signals must be connected to an external connector.
In a first phase, DESB constructs a gate net-list. In a second phase, DESB performs a functional analysis on this gate net-list to detect HZ nodes and short-circuit nodes.
This functional analysis depends on the 'n' parameter that defines the search depth.

OPTIONS
Options may be given in any order before or after the filename(s).

file2
    is the name of the vbe file to be generated. File1 is the default value.

-h  The functional abstraction can be accelerated if the '_s' convention is adopted. The user can indicate the signal flow when pass transistor are used in the circuit by adding the '_s' suffix to the output signal name. (This can be done directly in the layout).

-p=n
    This option sets the depth for the functional analysis process of DESB. This is the number of gates that will be taken into account, so that DESB can detect reconvergence in the circuit. The default value is 5.
    When n=0, the functional analysis process is desabled..

-v  When this option is set, the interface and the internal signal of the behavioural description are vectorized. Every bit of the vector has to be of the same type (in, out...for instance) otherwise the functional description will not be generated.

-i  This option makes desb read the 'inf' file. This file should have the same name than the input file and "inf' for extension. It may contain mutual exclusion conditions on ports of the circuit. These conditions are only used in the functional analysis process.
    # lines beginning with '#' are comment lines
    #    Syntax for the mutual exclusion conditions
        MUTEX
        muxUP{a,...,d};
        muxDN{m,...,p};
        cmpUP{i,...,l};
        cmpDN{x,...,z};
        END

muxUP
    expresses that one port at most in the list is "one".

muxDN
    expresses that one port at most in the list is "zero".

cmpUP
    expresses that one and only one port in the list is "one".

cmpDN
    expresses that one and only one port in the list is "zero".
    Port name may be preceded by the character '~' which minds that it is the inverse of the port which has to be taken into account.
    The user can also use this file to rename internal signals in the behavioural description in order to use the formal proof.
    #    Syntax to rename signals for the behavioural description
        RENAME
        existing_name : new_name ;
        *gno* : *latch_data* ;
        END
    "new_name" will replace "existing_name" in the behavioural description file. It is possible to use the joker '*'. When the names contain the string "gno", this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by l2_y_latch_data_01). Beware that only one rule can be applied to a name, (the following rules are then ignored when one has been applied) and that the rules are taken into account in the order in which they appear in the 'inf' file.

-nh When this option is set, a hierarchical netlist is generated. A behavioural description file is generated for every different gates, and a structural description of the circuit is created.

EXAMPLE
desb adder adder_x -v

OUTPUT FILES

vbe The functional description is described in a file called file1 or file2, with extension .vbe.

vst/hns
    The structural description when the 'nh' option is set.

dsbr
    Errors and warnings are reported in a file with extension .dsbr.

ENVIRONMENT VARIABLES

MBK_IN_LO
    indicates the format of the input net-list.
        spi    for    Spice net-list.
        fne    for    Compass extracted net-list.
        hns    for    Compass logical   net-list.
        al    for    Alliance extracted net-list.

MBK_OUT_LO
    indicates the format of the output net-list when the 'nh' option is set. MBK_IN_LO may take the value
        vst    for    Vhdl structural description
        hns    for     Compass logical net-list

MBK_WORK_LIB
    indicates where DESB has to read the input file and write the resulting files.

MBK_CATA_LIB
    If the input net-list is hierarchical, the leaf cells may not be in the working directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where DESB can find the cells.

MBK_VDD
    sets the name of power supply. "vdd" is the default. Every external port of the circuit whose name contain this string will be considered as a power supply.

MBK_VSS
    sets the name of the ground. "vss" is the default. Every external port of the circuit whose name contain this string will be considered as a ground.

VH_BEHSFX
    sets the extension of the file that will contain the VHDL description. "vbe" is the default value.

DESB_LANGUAGE
    When set to F, desb will report errors and warnings in French. when set to E, desb will report errors and warnings in English. The default is English.

SEE ALSO
logic(1), asimut(1), proof(1).

BUGS
Please, report problems or bugs to cao-vlsi@masi.ibp.fr

DIAGNOSTICS
"[WAR]    Drain of transistor is not connected"
indicates that a transistor drain which is connected to nothing has been found in the circuit.
"[WAR]    Source of transistor is not connected"
indicates that a transistor source which is connected to nothing has been found in the circuit.
"[WAR]    Transistor used as a diode"
means that a transistor with drain (or source) connected to gate has been found in the circuit, and the signal connecting them is neither power supply nor ground.
"[WAR]    Transistor used as a resistance"
means that a transistor P (resp. N) with gate connected to the ground (resp. power supply) has been found in the circuit.
"[WAR]    Transistor is never passing"
means that a transistor P (resp.N) with gate connected to power supply (resp. ground) has been found in the circuit.
"[WAR]    Transistor used as a capacitance"
indicates that a transistor with drain and source connected together as been found in the circuit.
"[WAR]    Transistor is (are) not used in the circuit"
means that these transistor are not used to pull up or pull down any transistor gate in the circuit, or any external port. This occurs if the output of an inverter does not drive anything: The both transistors of the inverter are not use from DESB point if view.
"[WAR]    Conflict may occur on signal"
This means that the signal may be pulled-up and pulled-down simultaneously. This is a warning since this message may disappear with a greater depth for the functional analysis process.
"[WAR]    HZ state may occur on signal"
This means that the signal is not pulled up or pulled down for every input pattern on the cone entries. This is a warning since this message may disappear with a greater depth for the functional analysis process.
"[ERR]    Transistor gate signal is not driven"
indicates that a transistor gate can not be pulled up nor pulled down.
"[ERR]    Gate of transistor is not connected"
indicates that a transistor gate which is connected to nothing has been found in the circuit.
"[ERR]    Loop detected between gate namei and gate namej"
means that a loop which does not correspond to a latch has been found in the circuit. Maybe the depth have not the right value, or maybe some conditions on external ports are missing in the 'inf' file.
"[ERR]    No VDD connector in the circuit"
means that desb did not find any external ports whose name is the name of power supply in the circuit. Has MBK_VDD the right value?
"[ERR]    No VSS connector in the circuit"
means that desb did not find any external ports whose name is the name of ground in the circuit. Has MBK_VSS the right value?
"[ERR]    Connector is power supply and ground"
means that DESB found a connector whose name includes MBK_VDD and MBK_VSS.