Real technology conversion
--------------------------

The purpose of ALLIANCE is to prevent the designer from using a single
technology. ALLIANCE wants portability and relies on a symbolic approach.
The whole chip is conceived with symbolic cells.

In order to send the chip to a specified foundry, the designer must
perform the symbolic to real conversion. This stage is the last stage of the
design methodology.

The only things you have to specify is the target technology and some
environment variables.

Target technology is prol12, a 1.2 process.
You can choose it by setting the RDS_TECHNO_NAME environment variable.

> setenv RDS_TECHNO_NAME /top/etc/prol12.rds

You also have to specify the format of the output file. ALLIANCE provides
two distinct formats: gds and cif.

> setenv RDS_OUT gds

This command instructs the converter to output the chip in GDSII.

A tricky thing is that symbolic pads must be replaced by their "real"
equivalent. You just have to set the RDS_IN environment variable.

> setenv RDS_IN gds

At last, you run the symbolic to real converter, s2r

> s2r -cv chip chip

first chip stands for chip.ap, the symbolic layout of the chip.
second chip stands for chip.gds, the generated file.
 
Press <return> to continue.
