Functional abstraction
----------------------

Now, something wonderful.

A VLSI designer is just like Asterix the Gaul. He is only afraid of
two things:
1) the sky falls on its head. 
2) its chip does not work.

desb, a functional asbtractor that extracts from a transistor netlist
a behavior, can relieve the designer from many headaches. From a transistor
netlist, desb finally outputs a VHDL file that can be simulated in turn.

the command is :

> desb -i -v chip

Then, you can simulate the resulting behavior file by issuing:

> asimut chip result1 result3 -b

result2.pat contains the results of the simulation.

Simulation of extracted behavior with asimut is not the only mean to see if the
chip is correct. The extracted behavior can also be used for formal proof. 
In ALLIANCE, Formal proof is the ultimate way to validate your circuit.

Before you can use proof, the formal prover, you must get acquainted with
some specific concepts of the formal proof theory. 

If you look at the extracted behavior, chip.vbe, you can notice that
desb has found four memorizing elements, specified as "reg_bit register".
In the formal proof, these four elements must match the four edge-triggered
latches of the former behavioral specification. 

If you examine the current directory, you will find a file called chip.inf. 
This file contains specific informations for desb. It instructs desb to 
rename the internal node name of every latch "core.l*" by its corresponding 
name in the first behavior file. In the cells/scr directory you can see 
that the name of the internal node of the used latch, ms_y.vbe, is dff_s. 
The equivalent name in addaccu.vbe is reg.

When you run desb with option -i, the program searches for the file chip.inf,
builds the gate netlist and replaces the node names by their equivalent names
in the behavior file, in order to make proof work.

Then, you can run proof, the formal prover:

> proof -d addaccu chip

Option -d displays logical functions as they are processed. 

Press <return> to continue.
