-- VHDL data flow description generated from `dlxm_sts`
--		date : Thu Jan 27 14:54:17 1994


-- Entity Declaration

ENTITY dlxm_sts IS
  PORT (
  ck : in BIT;	-- ck
  frz : in BIT;	-- frz
  reset : in BIT;	-- reset
  test : in BIT;	-- test
  ctlalu : in bit_vector(4 DOWNTO 0) ;	-- ctlalu
  opx_sign : in BIT;	-- opx_sign
  opy_sign : in BIT;	-- opy_sign
  alu_sign : in BIT;	-- alu_sign
  alu_nul : in BIT;	-- alu_nul
  alu_c31_n : in BIT;	-- alu_c31_n
  alu_c30_n : in BIT;	-- alu_c30_n
  ovr_en : in BIT;	-- ovr_en
  ico_en : in BIT;	-- ico_en
  rs : in bit_vector(4 DOWNTO 0) ;	-- rs
  rd : in bit_vector(4 DOWNTO 0) ;	-- rd
  rdrt : in bit_vector(4 DOWNTO 0) ;	-- rdrt
  mxrs_rdrt : in BIT;	-- mxrs_rdrt
  codop : in bit_vector(5 DOWNTO 0) ;	-- codop
  wenable_in : in bit_vector(8 DOWNTO 0) ;	-- wenable_in
  ctlrw_in : in bit_vector(3 DOWNTO 0) ;	-- ctlrw_in
  sr_mode : in BIT;	-- sr_mode
  sr_mask : in BIT;	-- sr_mask
  adr0 : in BIT;	-- adr0
  adr1 : in BIT;	-- adr1
  adr31 : in BIT;	-- adr31
  intrqs : in bit_vector(3 DOWNTO 0) ;	-- intrqs
  scin : in BIT;	-- scin
  alu_test : out BIT;	-- alu_test
  redpnt : out bit_vector(4 DOWNTO 0) ;	-- redpnt
  wrtpnt : out bit_vector(4 DOWNTO 0) ;	-- wrtpnt
  wenable_out : out bit_vector(5 DOWNTO 0) ;	-- wenable_out
  ctlrw_out : out bit_vector(3 DOWNTO 2) ;	-- ctlrw_out
  sr_ovr : out BIT;	-- sr_ovr
  sr_dav : out BIT;	-- sr_dav
  sr_iav : out BIT;	-- sr_iav
  sr_ico : out BIT;	-- sr_ico
  sr_it0 : out BIT;	-- sr_it0
  sr_it1 : out BIT;	-- sr_it1
  sr_it2 : out BIT;	-- sr_it2
  sr_it3 : out BIT;	-- sr_it3
  sr_reset : out BIT;	-- sr_reset
  rqs : out BIT;	-- rqs
  rw : out BIT;	-- rw
  rw_ctl : out BIT;	-- rw_ctl
  nfrz_ctl : out BIT;	-- nfrz_ctl
  byte : out bit_vector(3 DOWNTO 0) ;	-- byte
  scout : out BIT;	-- scout
  zero : out BIT;	-- zero
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END dlxm_sts;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF dlxm_sts IS
  SIGNAL ovr_r : REG_BIT REGISTER;	-- ovr_r
  SIGNAL ico_r : REG_BIT REGISTER;	-- ico_r
  SIGNAL dav_r : REG_BIT REGISTER;	-- dav_r
  SIGNAL iav_r : REG_BIT REGISTER;	-- iav_r
  SIGNAL it0_r : REG_BIT REGISTER;	-- it0_r
  SIGNAL it1_r : REG_BIT REGISTER;	-- it1_r
  SIGNAL it2_r : REG_BIT REGISTER;	-- it2_r
  SIGNAL it3_r : REG_BIT REGISTER;	-- it3_r
  SIGNAL reset_r : REG_BIT REGISTER;	-- reset_r
  SIGNAL freeze_r : REG_BIT REGISTER;	-- freeze_r
  SIGNAL aux80 : BIT;		-- aux80
  SIGNAL aux78 : BIT;		-- aux78
  SIGNAL aux76 : BIT;		-- aux76
  SIGNAL aux75 : BIT;		-- aux75
  SIGNAL aux74 : BIT;		-- aux74
  SIGNAL aux71 : BIT;		-- aux71
  SIGNAL aux69 : BIT;		-- aux69
  SIGNAL aux68 : BIT;		-- aux68
  SIGNAL aux61 : BIT;		-- aux61
  SIGNAL auxinit1 : BIT;		-- auxinit1
  SIGNAL aux120_a_a : BIT;		-- aux120_a_a
  SIGNAL aux77_a : BIT;		-- aux77_a
  SIGNAL aux92 : BIT;		-- aux92

BEGIN
  aux92 <= (not (ovr_r) and not (ico_r) and not (dav_r) and not (iav_r)
and not (aux68));
  aux77_a <= (wenable_in(8) or wenable_in(7) or (not (ovr_r) and not (aux76)));
  aux120_a_a <= ((not (adr31) and sr_mode) or not ((ctlrw_in(3) xor (not (ctlrw_in(0))
or ctlrw_in(2)))) or aux69 or not (aux92));
  auxinit1 <= (not (frz) and ck);
  aux61 <= (not ((not (ctlrw_in(2)) or ctlrw_in(0))) or (ctlrw_in(1) and
not ((not (ctlrw_in(0)) or ctlrw_in(2)))) or not ((ctlrw_in(1)
xor adr0)));
  aux68 <= ((not (codop(4)) and ico_en and (codop(1) or (codop(0) and not
((codop(5) xor codop(3))))) and (not (codop(1)) or (not (codop(5))
and codop(0) and not ((codop(3) and codop(2)))) or (codop(5)
and ((codop(3) and codop(2)) or (not (codop(0)) and not (codop(3)))))))
or (ico_en and codop(4) and ((not (codop(5)) and not (codop(1))
and codop(3)) or (codop(5) and codop(1) and sr_mode and (not
(codop(0)) or not (codop(3)))) or (codop(5) and codop(2) and
(codop(3) or codop(1))))));
  aux69 <= (ovr_en and (alu_c31_n xor alu_c30_n));
  aux71 <= (not (ctlrw_in(1)) and not ((not (ctlrw_in(0)) or ctlrw_in(2)))
and (not ((adr0 and adr1)) or (not (adr31) and sr_mode)));
  aux74 <= ((not (adr31) and sr_mode) or (not (ctlrw_in(1)) and not ((adr0
and adr1))));
  aux75 <= (not (ctlrw_in(3)) and not ((ctlrw_in(2) xor ctlrw_in(0))) and
aux74);
  aux76 <= (ico_r or dav_r or iav_r or aux69 or aux75 or (ctlrw_in(3) and
aux71) or aux68);
  aux78 <= ((not (codop(2)) and codop(4)) or (codop(5) and codop(1) and
(codop(4) or (not (codop(0)) and codop(2)))) or (not (codop(1))
and codop(3) and (codop(4) or (codop(5) and codop(0)))) or (not
(codop(4)) and ((not (codop(2)) and (not (codop(3)) or not (codop(5))))
or (codop(2) and codop(0) and not ((codop(5) xor codop(3)))))));
  aux80 <= ((not (opy_sign) and opx_sign) or (alu_sign and (not (opy_sign)
or opx_sign)));
  label0 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    freeze_r <= GUARDED ((test and it3_r) or (not (test) and frz));
  END BLOCK label0;
  label1 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    reset_r <= GUARDED ((test and freeze_r) or (not (test) and (reset or (not (wenable_in(7))
and reset_r))));
  END BLOCK label1;
  label2 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    it3_r <= GUARDED ((not (test) or it2_r) and (not (intrqs(3)) or test or (not (wenable_in(7))
and it3_r)));
  END BLOCK label2;
  label3 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    it2_r <= GUARDED ((not (test) or it1_r) and (not (intrqs(2)) or test or (not (wenable_in(7))
and it2_r)));
  END BLOCK label3;
  label4 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    it1_r <= GUARDED ((not (test) or it0_r) and (not (intrqs(1)) or test or (not (wenable_in(7))
and it1_r)));
  END BLOCK label4;
  label5 : BLOCK ((not (ck) and not (ck'STABLE)) = '1')
  BEGIN
    it0_r <= GUARDED ((not (test) or iav_r) and (not (intrqs(0)) or test or (not (wenable_in(7))
and it0_r)));
  END BLOCK label5;
  label6 : BLOCK ((not (auxinit1) and not (auxinit1'STABLE)) = '1')
  BEGIN
    iav_r <= GUARDED ((not (test) or dav_r) and (test or (not (wenable_in(7)) and
iav_r) or (ctlrw_in(3) and aux71)));
  END BLOCK label6;
  label7 : BLOCK ((not (auxinit1) and not (auxinit1'STABLE)) = '1')
  BEGIN
    dav_r <= GUARDED ((not (test) or ico_r) and (test or (not (wenable_in(7)) and
dav_r) or aux75));
  END BLOCK label7;
  label8 : BLOCK ((not (auxinit1) and not (auxinit1'STABLE)) = '1')
  BEGIN
    ico_r <= GUARDED ((not (test) or ovr_r) and (test or (not (wenable_in(7)) and
ico_r) or aux68));
  END BLOCK label8;
  label9 : BLOCK ((not (auxinit1) and not (auxinit1'STABLE)) = '1')
  BEGIN
    ovr_r <= GUARDED ((not (test) or scin) and (test or (not (wenable_in(7)) and ovr_r)
or aux69));
  END BLOCK label9;

zero <= '0';

scout <= not (reset_r);

byte(0) <= ((ctlrw_in(3) and ctlrw_in(1)) or not ((adr0 and adr1 and (not
(ctlrw_in(2)) or ctlrw_in(0)))) or aux120_a_a);

byte(1) <= (not (adr1) or aux61 or aux120_a_a);

byte(2) <= ((ctlrw_in(3) and ctlrw_in(1)) or not ((adr0 and (not (ctlrw_in(2))
or ctlrw_in(0)))) or not ((ctlrw_in(1) xor adr1)) or aux120_a_a);

byte(3) <= (not ((ctlrw_in(1) xor adr1)) or aux61 or aux120_a_a);

nfrz_ctl <= (frz and freeze_r);

rw_ctl <= (not (ck) or ctlrw_in(0) or (frz and freeze_r));

rw <= not (ctlrw_in(0));

rqs <= (ovr_r or reset_r or (sr_mask and (it0_r or it1_r or it2_r or
it3_r)) or aux76);

sr_reset <= reset_r;

sr_it3 <= it3_r;

sr_it2 <= it2_r;

sr_it1 <= it1_r;

sr_it0 <= it0_r;

sr_ico <= ico_r;

sr_iav <= iav_r;

sr_dav <= dav_r;

sr_ovr <= ovr_r;

ctlrw_out(2) <= ((ctlrw_in(2) and (wenable_in(8) or wenable_in(7))) or (ctlrw_in(2)
and not (aux69) and (not (ctlrw_in(0)) or ctlrw_in(3) or not
(aux74)) and aux92));

ctlrw_out(3) <= ((ctlrw_in(3) and (wenable_in(8) or wenable_in(7))) or (ctlrw_in(3)
and not (aux71) and not (aux69) and aux92));

wenable_out(0) <= (wenable_in(0) and aux77_a);

wenable_out(1) <= (wenable_in(1) and aux77_a);

wenable_out(2) <= (wenable_in(2) and aux77_a);

wenable_out(3) <= (wenable_in(4) and aux77_a);

wenable_out(4) <= (wenable_in(5) and aux77_a);

wenable_out(5) <= (wenable_in(6) and aux77_a);

wrtpnt(0) <= (wenable_in(3) or (rd(0) and aux78) or (rdrt(0) and not (aux78)));

wrtpnt(1) <= (wenable_in(3) or (rd(1) and aux78) or (rdrt(1) and not (aux78)));

wrtpnt(2) <= (wenable_in(3) or (rd(2) and aux78) or (rdrt(2) and not (aux78)));

wrtpnt(3) <= (wenable_in(3) or (rd(3) and aux78) or (rdrt(3) and not (aux78)));

wrtpnt(4) <= (wenable_in(3) or (rd(4) and aux78) or (rdrt(4) and not (aux78)));

redpnt(0) <= ((not (mxrs_rdrt) and rdrt(0)) or (rs(0) and mxrs_rdrt));

redpnt(1) <= ((not (mxrs_rdrt) and rdrt(1)) or (rs(1) and mxrs_rdrt));

redpnt(2) <= ((not (mxrs_rdrt) and rdrt(2)) or (rs(2) and mxrs_rdrt));

redpnt(3) <= ((not (mxrs_rdrt) and rdrt(3)) or (rs(3) and mxrs_rdrt));

redpnt(4) <= ((not (mxrs_rdrt) and rdrt(4)) or (rs(4) and mxrs_rdrt));

alu_test <= (not (ctlalu(0)) or ctlalu(4) or (ctlalu(3) and ctlalu(2) and
(ctlalu(1) or not (aux80))) or (not (ctlalu(2)) and not (alu_nul)
and not ((ctlalu(3) and (ctlalu(1) or not (aux80))))) or ((not
(ctlalu(3)) or ctlalu(1) or not (opy_sign) or opx_sign) and
((not (ctlalu(1)) and alu_nul) or (not (alu_nul) and ctlalu(1)
and (ctlalu(3) xor aux80)))));
END;
