SCLIB(5)

NAME

sclib
     - a portable CMOS Standard Cell Library

ORIGIN
This library belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu; 75252 PARIS Cedex 05; FRANCE
Fax: (33-1) 44.27.62.86; E-mail: cao-vlsi@masi.ibp.fr

SYNOPSIS

The library directory is defined by the environment variable MBK_CATA_LIB.

DESCRIPTION
 The symbolic layout approach is used for cell layout in order to provide process independance. As for alliance libraries the mapping to a specific process CIF or GDS2 layout is performed by s2r tool.
 Four files are attached to each cell :
- layout    cellname.ap
- transistor net-list    cellname.al
- VHDL behaviour    cellname.vbe
- postscript doc    cellname.ps
For each cell, you can get detailed information using "man cellname".
At the moment, sclib contains standard cells that have been developped at UPMC-MASI
It is possible to add new cells in the library just by providing the 3 files .ap, .al, .vbe in the standard cell directory.
The layout view can be created with the symbolic editor alc.
The topological constraints for the standard cell router scr are the abutment box size (height = 42 , width = 6 x n ), the metal1 VDD and VSS lines, the N well abutment, and I/Os in metal2 on south and north sides.
The net-list view can be automatically generated with the lynx extractor
The behavioural view can be checked with the desb functional abstractor. The file must contain the generic fields in order to be used by the logic synthesis tool logic and the I/Os terminals must be in the same order in the .vbe and .al files for genlib.
If you develop new cells, please send the corresponding files to cao-vlsi@masi.ibp.fr List of cells
--------------------------------------------------------------------------------------------
|    Description    Fanout    Name            |
--------------------------------------------------------------------------------------------
    => AND
      (A.B)    (drive=1)    a2_y
      (A.B)    (drive=2)    a2p_y
      (A.B.C)    (drive=1)    a3_y
      (A.B.C)    (drive=2)    a3p_y
      (A.B.C.D)    (drive=1)    a4_y
      (A.B.C.D)    (drive=2)    a4p_y
      /(A.B)    (drive=1)    na2_y
      /(A.B)    (drive=2)    na2p_y
      /(A.B.C)    (drive=1)    na3_y
      /(A.B.C)    (drive=2)    na3p_y
      /(A.B.C.D)    (drive=1)    na4_y
    => OR
       (A+B)    (drive=1)    o2_y
       (A+B)    (drive=2)    op2_y
       (A+B+C)    (drive=1)    o3_y
       (A+B+C)    (drive=2)    op3_y
       /(A+B)    (drive=1)    no2_y
       /(A+B)    (drive=2)    nop2_y
       /(A+B+C)    (drive=1)    no3_y
       /(A+B+C)    (drive=2)    nop3_y
    =>INV/BUF
       inv    (drive=1)    n1_y
       inv    (drive=2)    np1_y
       inv    (drive=4)    ndrv_y
       buf    (drive=2)    p1_y
       buf    (drive=4)    b1_y
    => T STATE
       3-state-inv    (drive=1)    tsn_y
       3-state-buf    (drive=1)    ts_y
    => XOR
       xor    (drive=1)    xr2_y
       nxor    (drive=1)    nxr2_y
    => COMPLEX
       /(AB+CD)    (drive=1)    nmx2_y
       /(A+B)(C+D)    (drive=1)    annup_y
       /((A+B)C)    (drive=1)    noa3_y
       /(AB+C)    (drive=1)    nao3_y
       /(ABC+D)    (drive=1)    nao4_y
    => LATCH
       latch one input    (drive=2)    l1_y
       latch one input (inverted)    (drive=1)    l1n_y
       latch two inputs    (drive=1)    l2_y
       latch two inputs (inverted)    (drive=1)    l2n_y
       latch three inputs    (drive=2)    l3_y
       latch two inputs + reset    (drive=1)    l3r_y
       latch two inputs + set    (drive=2)    l3s_y
       latch four inputs    (drive=2)    l4_y
       latch three inputs + reset    (drive=1)    l4r_y
       latch three inputs + set    (drive=1)    l4s_y
       latch five inputs    (drive=1)    l5_y
       latch four inputs + reset    (drive=2)    l5r_y
       latch four inputs + set    (drive=2)    l5s_y
       latch five inputs + reset    (drive=1)    l6r_y
       latch five inputs + set    (drive=3)    l6s_y
    =>FF
       one input master-slave    (drive=1)    ms_y
       one input master-slave (inverted)    (drive=1)    msn_y
       scannable master-slave    (drive=1)    ms2_y
       scannable master-slave(inverted)    (drive=1)    ms2n_y
    =>BUS
       bus hold    zbli_y
       pull-up    one_y
       pull-down    zero_y
       feed-through    tie_y
    =>MUX
       mux 2 to 1    (drive=1)    mx2_y
       mux 2 to 1    (drive=2)    mx2p_y
       mux 3 to 1    (drive=1)    mx3_y
    =>SPECIAL
       full-adder (sum)    (drive=1)    sum_y
       full-adder (carry)    (drive=1)    cry_y

SEE ALSO
MBK_CATA_LIB(1), scr(1), lynx(1), logic(1), desb(1), genlib(1), ap(1), al(1), vbe(1),

DIAGNOSTICS
If problems arise please e-mail to : cao-vlsi@masi.ibp.fr