LOGIC(1)

NAME

logic
    - Logic synthesis from a behavioural description (VHDL data flow)

ORIGIN
This software belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. and M. Curie
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
FAX: (33-1) 44.27.62.86 ; E-mail cao-vlsi@masi.ibp.fr

SYNOPSIS

logic [-o|-l|-s|-c]  data_flow_file output_file  [parameter_file]

DESCRIPTION
1 Input description
The behavioural description input (.vbe file) uses the same VHDL subset that the logic simulator asimut, the FSM synthesizer syf, the functional abstractor desb and formal prover proof (for further informations about the subset of VHDL, see the "vbe" manual).
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs : A bit signal can take the 'd' value. This value is interpreted as a '0' by the logic simulator asimut and the formal prover proof. Don't Cares are automatically generated by syf in the resulting '.vbe' file.
For the register signal, only one signal can appear in a guarded expression since the STABLE attribut is used. This attribut is supported only by technology mapping onto standard cells library as sclib.
logic divides the synthesis process into two main steps. The former optimizes the behavioural description using a Reduced Ordered Binary Decision Diagram representation of logic functions. Two kinds of optimization are performed : local or global. The second step performs technology mapping. The output netlist is constructed from a predefined standard cells library as SCLIB or by using a CMOS complex cells compiler called C4.
2 Mapping with SCLIB
All the cells appearing in the directory defined by the environment variable MBK_TARGET_LIB are used by logic since they are described in '.vbe' file. There are some restrictions about the type of the cell used. The cell must only have one output. For the combinational cells, two levels maximum (AND-OR or OR-AND) are required for the logical function. The cell must be characterized. The timing and area informations required by logic are specified in the "generic" clause of the ".vbe" file.
Generic list :
  area (in grids)
  load input for each input(in fempto-farad)
  resistance for each input (in ohm)
  propagate time for each input (in pico-second)
3 Mapping with C4
There is no predefined cell library. A decomposition phase is performed on the behavioural description such as each of the logic function are feasible by the C4 compiler. The C4 compiler then generates dynamically the cells througouht the following views : layout level, transistor level and characterized behavioural level. In the default mode, all the cells have the same height and topology as the SCLIB cells. So the synthesized block is still routable using SCR (or any standard cells router). C4 generates dual CMOS gates. The maximum number of serial transistors N (resp. P) is a parameter. The name of the cells generated by C4 is computed by a depth covering of the expression representing its associated logic function. The operator (o for OR, a for AND) is written in a prefixed notation while the arity (inputs number of the operator) is written in a postfixed notation. A "n" is added for the negative cells.
Example : F = not ((a and b) or c); name = noa22
Each cell generated by C4 is dynamically characterized with a RC model and the electrical informations are added to the behavioural description. A technology parameter file is used during this process.
4 Processing mode
logic can be used in batch mode or in interactive mode. The interactive mode is obtained when no option is given. This mode provides to create parameter files by modifying and copying the default parameter file.
5 Parameter file

Optimization mode : Five optimization modes can be used by the designer numbered 0 to 4. The mode 0 performs an area optimization while mode 4 performs a delay optimization. The others are a trade-off between these two extremes.

Optimization level : The quality of the obtained results (and of course the CPU time) increases with the optimization level (from 1 to 5).

Delayed inputs : Some primary inputs of the circuit can be delayed. By associating a delay in nano-second, the synthesis process takes them into account in order to optimize the global delay of the circuit.

Early outputs : Some outputs can be critical. They can be optimized in delay independently of the global mode of optimization.

Auxiliary signals saved : Some auxiliary signals can be saved.

C4 parameters : The maximum number of serial transistors in the N and P graph can be changed (from 2 to 6).
Default parameters :
  Optimization mode = 2 (50% area - 50% delay)
  Optimization level = 2
  Delayed input = 0
  Early output = 0
  Auxiliary signal saved = 0
  Number of serial transistors = 4 in N and P area

ENVIRONMENT VARIABLES

MBK_WORK_LIB gives the path for the input and output files (behavioural, structural and parameters description).

MBK_CATA_LIB gives auxiliary pathes for the input files (behavioural description).

MBK_TARGET_LIB gives the path (single) for the selected standard cells library.

MBK_C4_LIB gives the path (single) for the three views of each cell generated by C4.

MBK_IN_LO gives the format of models instantiated in the structural description.

MBK_OUT_LO gives the output format of the structural description.

MBK_OUT_PH gives the output format for the layout of the cells generated by C4.

MBK_NAME_LOG indicates that the behavioural and the structural files have the same file name.

OPTIONS
Only one option can be given at the same time.

-o optimizes globally a behavioural description.

-l optimizes locally a behavioural description.

-s maps a behavioural description onto a standard cells library.

-c maps a behavioural description with the CMOS Complex Cells Compiler : C4.

EXAMPLE
You can call logic as follows :
    logic -o alu4 area
        logic -s alu4d area

SEE ALSO
proof(1), desb(1), asimut(1), vhdl(5), scr(1), sclib(1).

DIAGNOSTICS
"VHDL : Error - bad usage of the 'stable' attribut"
The stable attribut must be used with only one signal in a guarded expression

BUGS
Please, report problems or bugs to cao-vlsi@masi.ibp.fr or more precisely to burgun@masi.ibp.fr