Simulation of the extracted chip netlist
----------------------------------------

Now, it's getting a little harder, because good design methodologies
rely on the simulation of the extracted netlist. ALLIANCE design
methodology do follow this good principle.

The extracted netlist with capacitances is chip.al, not chip.vst (the
original netlist).

The actual simulation relies on two points:
1) environment variables must be set correctly.
2) the pattern file that is to be used is addaccu.pat,
   the original pattern file .
   We do want here to compute the values of outputs, but
   to see if the extracted netlist outputs the right
   values.
 
Execution environment is set by issuing:

> setenv MBK_IN_LO al

because we want to use the extracted chip.al file.

Then you can run asimut by entering the following command:

> asimut chip addaccu result2

chip stands for chip.al
addaccu stands addaccu.pat, the pattern file with input and output values.
result2 stands for result2.pat, the generated file.

Errors during this execution mean that something went wrong between your
current position in the design flow and the behavioral simulation stage.

Press <return> to continue.
