PCK_P(1)

NAME
pck_p - clock pad, a cell of PAD-Lib (1.0)

SYNOPSIS

Genlib call
    LOINS ("pck_p","instance_name","I","CKS","CKM",
                   "VDDE","VDDI","VSSE","VSSI",0);

ORIGIN
This library belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu; 75252 PARIS Cedex 05; FRANCE
Fax: (33-1) 44.27.62.86; E-mail: cao-vlsi@masi.ibp.fr

DESCRIPTION

Clock pad generates two non-overlaping signals CKM and CKS, never at high state twogether from one signal I. The non-overlaping delay depends of temperature, process and load. This delay is obtained by six serial inverters (minimal size). It is recommanded to have at most two logical gates between one pck_p output and a register clock input. It is also necessary to balance CKM and CKS loads.

Typically, each output clock drives a set of NAND gates, with a register write enable signal too, and each NAND is followed by an inverter to drive the register clock input.

Aspect
            abutment-box : 244 lambdas x 401 lambdas
            +---------------------------------+
            |                                 |
            |                                 |
            |---------------------------------|
            |////////////// vsse /////////////|
            |---------------------------------|
            |---------------------------------|
            |////////////// vdde /////////////|
            |---------------------------------|
            |---------------------------------|
            |////////////// vddi /////////////|
            |---------------------------------|
            |---------------------------------|
            |////////////// vssi /////////////|
            |---------------------------------|
            |       +-+     +-+     +-+       |
            |       |I|     |O|     |O|       |
            +-------+-+-----+-+-----+-+-------+
                     I      CKM     CKS
            *--------+-------+-------+------------->
            0       40      60      168            x
                     1       2       2       lambdas in ALU1 (connectors)
                     2       2       2       lambdas in ALU2

Waveforms
                      ___________             ___________
           I : ______/           \___________/           \___

                            ________                _________
    real CKM : ____________/        \______________/

    vhdl CKM : __________________/\______________________/\__
               _________                ________
    real CKS :          \______________/        \____________
    vhdl CKS : ______/\______________________/\______________

Interface
    ENTITY pck_p IS
            PORT (
                    i    : in  BIT;
                    cks  : out BIT;
                    ckm  : out BIT;
                    vdde : in  BIT;
                    vddi : in  BIT;
                    vsse : in  BIT;
                    vssi : in  BIT;
            );

Behaviour
            cks <=      i  and not i'STABLE;
            ckm <= not (i) and not i'STABLE;
            ASSERT  ((vddi='1')and(vdde='1')and(vssi='0')and(vsse='0'))
            REPORT "Power supply is missing on PCK_P"
            SEVERITY WARNING;

FILES

padname.vbe
    behavioral view in VHDL-language, used by the logical simulator asimut(1).

padname.al
    extracted transistor netlist, this netlist is issued from the real layout and should content all transistors and capacities.

padname.ap
    physical view in symbolic layout, it is used by the padring router. It just contents, pins and some layers to connect them.

SEE ALSO

sclib(5), genlib(1),

BUGS
Please report bugs, problems and suggestions to