FSM(5)

NAME

fsm
VHDL Finite State Machine subset.

ORIGIN
ALLIANCE CAD system from the CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr

DESCRIPTION

This document describes the ALLIANCE VHDL subset for Finite State Machine description.
This FSM subset is not accepted by the logic simulator ASIMUT(see asimut(1)), and the formal prover PROOF(see proof(1)).
This VHDL subset is defined to enable classical MOORE and MEALEY synchronous finite state machine description as well as stack FSM description (see syf(1) for further information about this kind of FSM). A scan-path for state registers can also be specified.
The FSM VHDL subset allows the use of process. On the other hand reg_bit, reg_vector and bus types are not supported.
FSM's states and stack control signals are declared as enumerated type.
For the scan-path, three more signals are required:
    - test_mode: in bit.
    - scan-in: in bit.
    - scan-out: out bit.

These signals declared in interface, are not used nor assigned in the FSM description. the '-scan' option of syf(1) allows scan-path implementation: If test_mode is true then, the LSB of the state registers is assigned by scan-in (scan-in must take value from MSB to LSB of the state code to be set in the state registers). scan-out is assigned by the MSB of the state registers.
If '-scan' option is not used and scan-path pragmas are defined, syf(1) assigns scan-in to the scan-out.

Pragma :
    Pragma is a comment which gives useful informations to the synthesis tool SYF.
    Three pragmas are used, these generic names are :
        - CLOCK : External clock signal name.
        - CUR_STATE : Current State name.
        - NEX_STATE : Next State name.

Eight other pragmas are optional.
Three pragmas are required only for scan-path implementation.
    - TEST_MODE : Enable test mode (scan-path).
    - SCIN : scan-path input.
    - SCOUT : scan-path output.

Five other are used only in a STACK FSM.
    - RET_STATE : Return State name.
    - CONTROL : Stack Control signal name.
    - POP : POP operation on the stack.
    - PUSH : PUSH operation on the stack.
    - NOP : NOP operation on the stack.

Two different processes are used : The first process, called state process
allows to describe state transition and outputs generation. It is not controled by the clock. The second process controled by the clock and descibes the state register and stack registers modifications.
State process sensitivity list contains inputs and CURRENT_STATE, it means that state process is activated when CURRENT_STATE or input signal is removed. A case statement is used to describe, for each state, the next state and outputs.
The second process sensitivity list contains the clock signal, so this process is enabled whenever clock signal is assigned a new value. Both Level sensitive latch, and falling edge triggered flip flop can be used for
 state registers and stack implementation.

EXAMPLES

Entity FSM_EX is
    port(
ck : in bit ;
reset:in bit;
t_mode:in bit;
s_in:in bit;
I:in bit;
s_out:out bit;
o:out bit
);
End FSM_EX;
architecture auto of FSM_EX is
type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
type CONTROL is (PUSH,POP,NOP);
-- pragma CLOCK ck
-- pragma CUR_STATE CURRENT_STATE
-- pragma NEX_STATE NEXT_STATE
-- pragma RET_STATE RETURN_STATE
-- pragma CONTROL CTRL
-- pragma PUSH PUSH
-- pragma POP POP
-- pragma NOP NOP
-- pragma TEST_MODE t_mode
-- pragma SCIN s_in
-- pragma SCOUT s_out
signal CURRENT_STATE, NEXT_STATE, RETURN_STATE : STATE_TYPE;
signal CTRL : CONTROL;
signal STACK_0, STACK_1 : STATE_TYPE ;
begin

PROCESS(CURRENT_STATE,reset)
	begin
		if(reset) then
			NEXT_STATE <= S0 ;
			o <= '0' ;
	else
    	case CURRENT_STATE is
  			WHEN S0 =>
				NEXT_STATE <= S1;
				RETURN_STATE <= S5;
				CTRL <= PUSH;
				o <= '0';
  			WHEN S1 =>
				if (I = '1') then
					NEXT_STATE <= S2;
					CTRL <= NOP;
				else
					NEXT_STATE <= S3;
					CTRL <= NOP;
				end if;
				o <= '0';
  			WHEN S2 =>
				NEXT_STATE <= S4;
				CTRL <= NOP;
				o <= '0';
  			WHEN S3 =>
				NEXT_STATE <= S4;
				CTRL <= NOP;
				o <= '0';
  			WHEN S4 =>
				NEXT_STATE <= STACK_0;
				CTRL <= POP;
				o <= '1';
  			WHEN S5 =>
				if (I = '1') then
					NEXT_STATE <= S1;
					RETURN_STATE <= S0 ;
					CTRL <= PUSH;
				else
					NEXT_STATE <= S5;
					CTRL <= NOP;
				end if ;
				o <= '0';
 			WHEN others =>
				assert ('1')
				report "illegal state";
		end case;
	end if ;
end process;
process(ck)
	begin
		if(ck = '0' and not ck' stable) then
			CURRENT_STATE <= NEXT_STATE;
			case CTRL is
				WHEN POP =>
					STACK_0 <= STACK_1;
				WHEN PUSH =>
					STACK_1 <= STACK_0;
					STACK_0 <= RETURN_STATE;
				WHEN NOP =>
					NULL;
			end case;
		end if;
end process;
end auto;

SEE ALSO

vbe(5), syf(1)

BUGS

Please e-mail to cao-vlsi@masi.ibp.fr for bug report and suggestions.