/****************************************************************************/
/*                                                                          */
/*                      Chaine de CAO & VLSI   Alliance                     */
/*                                                                          */
/*    Produit : synthetiseur logique                                        */
/*    Fichier : flatpol.c                                                      */
/*                                                                          */
/*    (c) copyright 1991 Laboratoire MASI equipe CAO & VLSI                 */
/*    Tous droits reserves                                                  */
/*    Support : e-mail cao-vlsi@masi.ibp.fr                                 */
/*                                                                          */
/*    Auteur(s) : L. Burgun                             le : 31/01/1992     */
/*                                                                          */
/*    Modifie par :                                     le : ../../....     */
/*    Modifie par :                                     le : ../../....     */
/*    Modifie par :                                     le : ../../....     */
/*                                                                          */
/****************************************************************************/

#include MUT_H
#include LOG_H
#include BEH_H

/*-------------------------------------------------------------------------
flatPolarityBeh	: reporte les inverseurs sur une befig. 
---------------------------------------------------------------------------
retour		: un void.
---------------------------------------------------------------------------*/
void flatPolarityBeh(beh)
befig_list *beh;
{
beout_list *out;
beaux_list *aux;
bereg_list *reg;
bebus_list *bus;
bebux_list *bux;
biabl_list *biabl;
chain_list *expr;

out = beh->BEOUT;
while (out)
   {
   if (out->ABL)
      {
      expr = flatPolarityExpr(out->ABL,1);
      freeExpr(out->ABL);
      out->ABL = expr;
      }
   out = out->NEXT;
   }

aux = beh->BEAUX;
while (aux)
   {
   if (aux->ABL)
      {
      expr = flatPolarityExpr(aux->ABL,1);
      freeExpr(aux->ABL);
      aux->ABL = expr;
      }
   aux = aux->NEXT;
   }

reg = beh->BEREG;
while (reg)
   {  
   biabl = reg->BIABL;
   while (biabl)
      {
      if (biabl->CNDABL && biabl->VALABL)
         {
         expr = flatPolarityExpr(biabl->CNDABL,1);
         freeExpr(biabl->CNDABL);
         biabl->CNDABL = expr;
         expr = flatPolarityExpr(biabl->VALABL,1);
         freeExpr(biabl->VALABL);
         biabl->VALABL = expr;
         }
      biabl = biabl->NEXT;
      }
   reg = reg->NEXT;
   }  
      
bus = beh->BEBUS;
while (bus)
   {  
   biabl = bus->BIABL;
   while (biabl)
      {
      if (biabl->CNDABL && biabl->VALABL)
         {
         expr = flatPolarityExpr(biabl->CNDABL,1);
         freeExpr(biabl->CNDABL);
         biabl->CNDABL = expr;
         expr = flatPolarityExpr(biabl->VALABL,1);
         freeExpr(biabl->VALABL);
         biabl->VALABL = expr;
         }
      biabl = biabl->NEXT;
      }
   bus = bus->NEXT;
   }  

bux = beh->BEBUX;
while (bux)
   {  
   biabl = bux->BIABL;
   while (biabl)
      {
      if (biabl->CNDABL && biabl->VALABL)
         {
         expr = flatPolarityExpr(biabl->CNDABL,1);
         freeExpr(biabl->CNDABL);
         biabl->CNDABL = expr;
         expr = flatPolarityExpr(biabl->VALABL,1);
         freeExpr(biabl->VALABL);
         biabl->VALABL = expr;
         }
      biabl = biabl->NEXT;
      }
   bux = bux->NEXT;
   }  
}
