RAGE(1)

NAME
rage - Random Acess Memory(RAM) Generator

ORIGIN
This software belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. & M. Curie
4, Place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr

SYNOPSIS
rage bits words [ -n | -m | -w ] [ -u ] [ -tn ] [ layout ] [ outline ] [ vhdl ] [ data ] [ icon ] [ name=blockname ]

DESCRIPTION
rage generates several different views of a Random Acess Memory. The ram generated is always constitued of two ram-cells blocks between which is placed a decoder cell.

The interfaces of the ram are given below(there is two versions of the interface because input and output data can be bidirectionnal or separated):
bidirectionnal data:
ENTITY rage IS

PORT(adr: IN BIT_VECTOR(0 TO n);
    data: INOUT BIT_VECTOR(0 TO w);
    ck: IN BIT;
    write: IN BIT;
    vdd: IN BIT;
    vss: IN BIT);

END rage;
unidirectionnal data:
ENTITY rage IS

PORT(adr: IN BIT_VECTOR(0 TO n);
    din: IN BIT_VECTOR(0 TO w);
    dout: OUT BIT_VECTOR(0 TO w);
    ck: IN BIT;
    write: IN BIT;
    vdd: IN BIT;
    vss: IN BIT);

END rage;

OPTIONS

bits
    is the number of bits per word. The range is from 2 to 128, and this number must be even.

words
    indicates the size of the ram in power of 2 (ex: 8 --> 256 words)

-n|-m|-w
    specifies the aspect/ratio of the generated block. In fact, this generator is designed on the base of:

    - 3 line decoders: 6 --> 64, 7 --> 128, 8 --> 256
    - 4 column decoders(multiplexers): 2 --> 1, 4 -->1, 8 --> 1, 16 --> 1
    Then, we obtain the following table, corresponding to all the possibilities of our generator:
          -------------------------
          | mux |
          |-----------------------|
          | 1 | 2 | 3 | 4 |
     -----|-----------------------|
     | 6 | 128 | 256 | 512 | 1024|
     |----|-----------------------|
     | 7 | 256 | 512 | 1024| 2048|
     |----|-----------------------|
     | 8 | 512 | 1024| 2048| 4096|
     ------------------------------
    for example: in this configuration we will have three versions of the 1K-word ram.
    - the first is a 256x4: which is narrow
    - the second is a 128x8: which is medium
    - the third is a 64x16: which is wide
    So, the -n,-m and -w parameters correspond to the different ways of implementation of the ram size regarding to that we want the narrow, the medium or the wide version.
    Note: However, there is some cases where the choose is limited and can be not possible(extremity sizes, for ex.)

-u  specifies that the input and output data buses must be separated (unidirectionnal)

-tn allows the insertion of one or two allow-ALU2 across the ram (one or two with each bit). n=1 or 2.

layout
    generates the layout view of the ram

vhdl
    gives a vhdl description of the ram

outline
    generates only an outline layout of the ram with physical connectors.

data
    provides technical and design informations about the ram like size values, function chronograms and propagation delays.

name=blockname
    specifies the name of the generated ram (default name is ram<bits>_<word>)

icon
    Provides a VTI schematic compatible icon representing the generated RAM with connectors.

EXAMPLES

    rage 64 10 -m -u layout vhdl data name=memo

produces the layout and vhdl views of a 1K size ram of 64-bits word , medium aspect/ratio and separated data buses named "memo" and provides informations about its function, timing and layout charachteristics.

SEE ALSO
MBK_CATA_LIB(1), MBK_WORK_LIB(1), MBK_OUT_PH(1), MBK_OUT_LO(1), MBK_IN_PH(1),

DIAGNOSTICS
Please report bugs, problems and suggestions to cao-vlsi masi.ibp.fr