
/*
 *
 */

static rsa_vhdl(n,cin,cout,over,overn,not,csa,sub,addsub,
                deci,stretch,stretch2,name,msb0)
int n,cin,cout,over,overn,not,csa,sub,addsub,
    deci,stretch,stretch2,msb0;
char  *name ;
{
 int  d=msb0?0:n-1;
 int  f=msb0?n-1:0;
 int  l=n-1;
 int  p;
 int  i;
 FILE *fvhdl;
 int  j;
 char *updown;


   if ( stretch || stretch2 || deci )
      printf("Warning : options deci, stretch, stretch2 are not taken into account for vhdl view\n");

   mbkenv() ;

   fvhdl = (FILE *)mbkfopen( name, "vbe", "w" ) ;

   updown=msb0?NAME("to"):NAME("downto");

               fprintf( fvhdl, "\nentity %s is\n\n", name ) ;
               fprintf( fvhdl, "   port (    a : in  BIT_VECTOR( %3d %s %3d ) ;\n",d,updown,f ) ;
               fprintf( fvhdl, "             b : in  BIT_VECTOR( %3d %s %3d ) ;\n",d,updown,f ) ;
   if( csa )   fprintf( fvhdl, "             c : in  BIT_VECTOR( %3d %s %3d ) ;\n",d,updown,f ) ;
   if( cin )   fprintf( fvhdl, "           cin : in  BIT ;\n" ) ;
   if( cout )  fprintf( fvhdl, "            co : out BIT_VECTOR( %3d %s %3d ) ;\n",d,updown,f ) ;
   if( csa )   fprintf( fvhdl, "           coc : out BIT ;\n" ) ;
               fprintf( fvhdl, "          cout%s : out BIT ;\n", (rsa_puiss(n-1)&1) ? "" : "_n" ) ;
   if( over || overn )
               fprintf( fvhdl, "          over%s : out BIT ;\n", (rsa_puiss(n-2)&1) ? "" : "_n" ) ;
               fprintf( fvhdl, "             s : out BIT_VECTOR( %3d %s %3d ) ;\n",d,updown,f ) ;
   if(addsub)  fprintf( fvhdl, "           sub : in BIT ;\n");
               fprintf( fvhdl, "           vdd : in BIT ;\n");
               fprintf( fvhdl, "           vss : in BIT");
               fprintf( fvhdl, " ) ;\n\nend %s ;\n\n\n", name ) ;

               fprintf( fvhdl, "architecture DATA_FLOW of %s is\n\n", name ) ;
               fprintf( fvhdl, "   signal  ina : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  inb : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  ins : BIT_VECTOR( 0 to %3d ) ;\n", l);
   if( cout)   fprintf( fvhdl, "   signal  ico : BIT_VECTOR( 0 to %3d ) ;\n", l);
   if( sub )   fprintf( fvhdl, "   signal  isb : BIT_VECTOR( 0 to %3d ) ;\n", l);
   if(addsub)  fprintf( fvhdl, "   signal  xr2 : BIT_VECTOR( 0 to %3d ) ;\n", l);
   if( csa ) { fprintf( fvhdl, "   signal  car : BIT_VECTOR( 0 to %3d ) ;\n", n);
               fprintf( fvhdl, "   signal  inc : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  xr3 : BIT_VECTOR( 0 to %3d ) ;\n", l);}
               fprintf( fvhdl, "   signal  ada : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  adb : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  ads : BIT_VECTOR( 0 to %3d ) ;\n", l);
               fprintf( fvhdl, "   signal  icp : BIT_VECTOR( 0 to %3d ) ;\n", n);
               fprintf( fvhdl, "\nbegin\n\n" ) ;
/* Interface */
               fprintf( fvhdl, "   ina(   0 to %3d ) <=   a( %3d %s %3d ) ;\n", l,d,updown,f);
               fprintf( fvhdl, "   inb(   0 to %3d ) <=   b( %3d %s %3d ) ;\n", l,d,updown,f);
               fprintf( fvhdl, "     s( %3d %s %3d ) <= ins(   0 to %3d ) ;\n", d,updown,f,l);
   if( csa )   fprintf( fvhdl, "   inc(   0 to %3d ) <=   c( %3d %s %3d ) ;\n", l,d,updown,f);
   if( cout)   fprintf( fvhdl, "    co( %3d %s %3d ) <= ico(   0 to %3d ) ;\n", d,updown,f,l);

/* First stage */

   if( csa ) { fprintf( fvhdl, "   car( %3d ) <= '0' ;\n\n", n ) ;
               fprintf( fvhdl, "   xr3( 0 to %3d ) <= ina( 0 to %3d ) xor inb( 0 to %3d ) xor inc( 0 to %3d ) ;\n\n", l,l,l,l);
               fprintf( fvhdl, "   car( 0 to %3d ) <=    ( ina( 0 to %3d ) and inb( 0 to %3d ) )\n"    ,l,l,l);
               fprintf( fvhdl, "                      or ( ina( 0 to %3d ) and inc( 0 to %3d ) )\n"    ,l,l  );
               fprintf( fvhdl, "                      or ( inb( 0 to %3d ) and inc( 0 to %3d ) ) ;\n\n",l,l  ); }
   if( sub )   fprintf( fvhdl, "   isb( 0 to %3d ) <= not inb( 0 to %3d ) ;\n\n", l,l);
   if(addsub)  for(j=0;j<n;j++)
               fprintf( fvhdl, "   xr2( %3d ) <= sub xor inb( %3d ) ;\n", j,j);
               fprintf( fvhdl, "\n\n");
/* Connection */

   if( csa ) { fprintf( fvhdl, "   ada( 0 to %3d ) <= xr3( 0 to %3d ) ;\n", l,l);
               fprintf( fvhdl, "   adb( 0 to %3d ) <= car( 1 to %3d ) ;\n", l,n); }
   else
   if( sub ) { fprintf( fvhdl, "   ada( 0 to %3d ) <= isb( 0 to %3d ) ;\n", l,l);
               fprintf( fvhdl, "   adb( 0 to %3d ) <= ina( 0 to %3d ) ;\n", l,l); }
   else
   if(addsub){ fprintf( fvhdl, "   ada( 0 to %3d ) <= xr2( 0 to %3d ) ;\n", l,l); 
               fprintf( fvhdl, "   adb( 0 to %3d ) <= ina( 0 to %3d ) ;\n", l,l); } 
   else      { fprintf( fvhdl, "   ada( 0 to %3d ) <= ina( 0 to %3d ) ;\n", l,l);  
               fprintf( fvhdl, "   adb( 0 to %3d ) <= inb( 0 to %3d ) ;\n", l,l); }

/* Adder */

               fprintf( fvhdl, "\n ads( 0 to %3d ) <= ada( 0 to %3d ) xor adb( 0 to %3d ) xor icp( 1 to %3d ) ;\n\n",l,l,l,n);
               fprintf( fvhdl, "   icp( 0 to %3d ) <=    ( ada( 0 to %3d ) and adb( 0 to %3d ) )\n"    ,l,l,l);
               fprintf( fvhdl, "                      or ( ada( 0 to %3d ) and icp( 1 to %3d ) )\n"    ,l,n  );
               fprintf( fvhdl, "                      or ( adb( 0 to %3d ) and icp( 1 to %3d ) ) ;\n\n",l,n  );
   if( cin )   fprintf( fvhdl, "   icp( %3d ) <= cin ;\n", n);
   else
   if( sub )   fprintf( fvhdl, "   icp( %3d ) <= '1' ;\n", n);
   else
   if(addsub)  fprintf( fvhdl, "   icp( %3d ) <= sub ;\n", n);
   else        fprintf( fvhdl, "   icp( %3d ) <= '0' ;\n", n);

/* Outputs */

               fprintf( fvhdl, "\n   ins( 0 to %3d ) <=%sads( 0 to %3d ) ;\n\n", n-1, not ? " not " : " ", n-1 ) ;

   if( csa )   fprintf( fvhdl, "   coc  <= car( 0 ) ;\n" ) ;

               p = rsa_puiss( n ) ;
               if( rsa_restp( n, p ) != 0 )   p++ ;
               if( p & 1 ) fprintf( fvhdl, "   cout_n <= not icp( 0 ) ;\n" ) ;
               else        fprintf( fvhdl, "   cout <= icp( 0 ) ;\n" ) ;

   if( over || overn )
               fprintf( fvhdl, "   over%s <= %s icp( 1 ) ; \n",
                        (rsa_puiss(n-2)&1) ? "" : "_n", (rsa_puiss(n-2)&1) ? "" : "not" ) ;

   if( cout )  fprintf( fvhdl, "\n   ico( 0 to %3d ) <= icp( 0 to %3d ) ;\n", l, l ) ;
               fprintf( fvhdl, "\n" ) ;
               fprintf( fvhdl, "   ASSERT (vss = '0')\n   REPORT \"Power supply is missing on vss !!!\"\n   SEVERITY ERROR;\n");
               fprintf( fvhdl, "   ASSERT (vdd = '1')\n   REPORT \"Power supply is missing on vdd !!!\"\n   SEVERITY ERROR;\n");

               fprintf( fvhdl, "\nend DATA_FLOW ;\n" ) ;
   fclose( fvhdl ) ;
}


/*
 * OLD
 */

/* if( deci ) { int  bitslice ; int j ;
 *              bitslice = n-4 ;  
 *              for( j = 3 ; j < n ; j+=4, bitslice-=4 )
 *                 fprintf( fvhdl, "          deci%d%s : out BIT ;\n", bitslice, (rsa_puiss(j)&1) ? "" : "_n" ) ;
 *              fprintf( fvhdl, "\n" ) ;
 *            }
 */
/*for( j = (~n)&1 ; j < n ; j += 2 )
  *            fprintf( fvhdl, "          vdd%d : in BIT ;\n", j ) ;
  *            fprintf( fvhdl, "          vss%d : in BIT", n&1 ) ;
  *for( j = (n&1)+2 ; j <= n ; j += 2 )
  *            fprintf( fvhdl, " ;\n          vss%d : in BIT", j ) ;
  */
/* if( deci ) { int  bitslice ; int j ;
 *              bitslice = n-4 ;
 *              for( j = 3 ; j < n ; j+=4, bitslice-=4 )  
 *                 fprintf( fvhdl, "   deci%d%s <= %s icp( %3d ) ; \n", bitslice,
 *                          (rsa_puiss(n-1)&1) ? "" : "_n", (rsa_puiss(n-1)&1) ? "" : "not", bitslice ) ;
 *            }
 * else       {
 */
/*             p = rsa_puiss( n ) ;
 *             if( rsa_restp( n, p ) != 0 )   p++ ;
 *             if( p & 1 ) fprintf( fvhdl, "   cout_n <= not icp( 0 ) ;\n" ) ;
 *             else        fprintf( fvhdl, "   cout <= icp( 0 ) ;\n" ) ;
 */
 /*
  *           }
  */
/*
   for( j = n&1 ; j <= n ; j += 2 )
               fprintf( fvhdl,
                    "   ASSERT (vss%d = '0')\n   REPORT \"Power supply is missing on vss%d !!!\"\n   SEVERITY ERROR;\n", j, j );
   for( j = (~n)&1 ; j < n ; j += 2 )
               fprintf( fvhdl,
                    "   ASSERT (vdd%d = '1')\n   REPORT \"Power supply is missing on vdd%d !!!\"\n   SEVERITY ERROR;\n", j, j );
*/
