ENTITY addaccu IS

PORT( 
  a0 : in BIT ;
  a1 : in BIT ;
  a2 : in BIT ;
  a3 : in BIT ;
  b0 : in BIT ;
  b1 : in BIT ;
  b2 : in BIT ;
  b3 : in BIT ;
  sel : in BIT ;
  ck : in BIT ;
  s0 : out BIT ;
  s1 : out BIT ;
  s2 : out BIT ;
  s3 : out BIT ;
  vdd,vss : in BIT ;
  vdde, vsse : in BIT
);

END addaccu;

ARCHITECTURE fonctional OF addaccu IS

SIGNAL muxsor, regsor, sum : BIT_VECTOR(0 to 3) ;
SIGNAL carry : BIT_VECTOR(0 to 2) ;
SIGNAL reg0 : reg_bit register;
SIGNAL reg1 : reg_bit register;
SIGNAL reg2 : reg_bit register;
SIGNAL reg3 : reg_bit register;

BEGIN

ASSERT(vdd = '1' and vss = '0')
   REPORT "Wrong power supplies"
   SEVERITY WARNING;

ASSERT(vdde = '1' and vsse = '0')
   REPORT "Wrong power external supplies"
   SEVERITY WARNING;

  WITH sel SELECT
    muxsor(0) <= a0 WHEN '0', regsor(0) WHEN '1' ;
  WITH sel SELECT
    muxsor(1) <= a1 WHEN '0', regsor(1) WHEN '1' ;
  WITH sel SELECT
    muxsor(2) <= a2 WHEN '0', regsor(2) WHEN '1' ;
  WITH sel SELECT
    muxsor(3) <= a3 WHEN '0', regsor(3) WHEN '1' ;

  sum(0) <= muxsor(0) xor b0 ;
  carry(0) <= muxsor(0) and b0 ;

  sum(1) <= muxsor(1) xor b1 xor carry(0) ;
  carry(1) <= (muxsor(1) and b1) or
              (muxsor(1) and carry(0)) or
              (b1 and carry(0)) ;

  sum(2) <= muxsor(2) xor b2 xor carry(1) ;
  carry(2) <= (muxsor(2) and b2) or
              (muxsor(2) and carry(1)) or
              (b2 and carry(1)) ;

  sum(3) <= muxsor(3) xor b3 xor carry(2) ;

  s0 <= sum(0) ;
  s1 <= sum(1) ;
  s2 <= sum(2) ;
  s3 <= sum(3) ;

  L0 : BLOCK ((ck = '0') and not ck'STABLE)
     BEGIN
     reg0 <= GUARDED not sum(0) ;
     reg1 <= GUARDED not sum(1) ;
     reg2 <= GUARDED not sum(2) ;
     reg3 <= GUARDED not sum(3) ;
  END BLOCK ;

  regsor(0) <= not reg0 ;
  regsor(1) <= not reg1 ;
  regsor(2) <= not reg2 ;
  regsor(3) <= not reg3 ;
END; 
