PROL(5)

NAME
prol - define the rules for symbolic to real layout translation

ORIGIN
This software belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr

DESCRIPTION
This file describes the rules used by the mbk(1) to rds translator. In the following file, symbolic layout objects are refered as mbk(1) objects, mbk(1) being the internal data structure that supports symbolic representation. On the other hand, rds is a data structure describing mainly rectangles, and is therefore used for real layout representation.

Some syntaxic remarques on the way to write the file follow. The case of identifiers is not significant, so NDIF is equivalent to NdiF. Comments are allowed anywhere in the file, using the sharp (#) as start of comment, and newline as end of comment. A line begining with a sharp will be ignored, and a line containing a sharp will be read up to the character preeceding it. A newline can be escaped using the backslash ( followed by the newline. If some character, spaces or tabs for example, follow the backslash, chances are that a syntax error will be issued.

First, some important process parameters are needed, the physical grid step, that is the least common multiple of all the technologies values in terms of layout distances, and the lambda, computed from a careful observation of the process design rules.
Then, a set of tables is needed, to describe how to translate a symbolic object, belonging to the mbk(1) world, and a set of layout rectangles, in rds.
Each table has a special meaning, and its parametrization exend beeing not full, some borders are to be evocated. Several type of table exists indeed. Some are needed for object translation, others for post treatment parametrization, others to define cif or gds identifiers regarding rds ones.
Many things seem to be parametrizable, but in fact, mostly, if not only, numbers, names in cif and gds translation tables, and boolean value in post treatement may be changed without problems.

For any table, if some layer is not applicable, it can simply be omitted. The default action is `do nothing', or use a value of 0.0 for all entries.

LAYERS AND PATTERNS
Since the goal of this file is to allow translation from mbk(1) to rds, the meaning of the layers in both representation shall be known.
Mbk layers

    NWELL
        minimum width 4 ; N-well.

    PWELL
        minimum width 4 ; P-well.

    NTIE
        minimum width 2 ; N diffusion for polarisation.

    PTIE
        minimum width 2 ; P diffusion for polarisation.

    NDIF
        minimum width 2 ; N diffusion for transistor.

    PDIF
        minimum width 2 ; P diffusion for transistor.

    NTRANS
        minimum width 1 (gate width) ; N transistor.

    PTRANS
        minimum width 1 (gate width) ; P transistor.

    POLY
        minimum width 1 ; polysilicon, not transistor gate.

    ALU1
        minimum width 1 ; first level of metal.

    ALU2
        minimum width 2 ; second level of metal.

    ALU3
        minimum width 3 ; third level of metal (unused).

    TPOLY
        minimum width 1 ; through route for POLY.

    TALU1
        minimum width 1 ; through route for ALU1.

    TALU2
        minimum width 2 ; through route for ALU2.

    TALU3
        minimum width 3 ; through route for ALU3 (unused).
Mbk patterns

    CONT_POLY
        cut pattern from ALU1 to POLY

    CONT_VIA
        cut pattern from ALU1 to ALU2

    CONT_VIA2
        cut pattern from ALU2 to ALU3

    CONT_DIF_N
        cut pattern from ALU1 to NDIF

    CONT_DIF_P
        cut pattern from ALU1 to PDIF

    CONT_BODY_N
        cut pattern from ALU1 to NTIE

    CONT_BODY_P
        cut pattern from ALU1 to PTIE

    C_X_N
        corner primitive for L or S shaped N transistor

    C_X_P
        corner primitive for L or S shaped P transistor
Rds layers

    RDS_NWELL
        N-well (or N-tub), bulk for P transistors.

    RDS_PWELL
        P-well (or P-tub), bulk for N transistors.

    RDS_NDIF
        use for symbolic extractor as equivalent of NDIF.

    RDS_PDIF
        use for symbolic extractor as equivalent of PDIF.

    RDS_NTIE
        use for symbolic extractor as equivalent of NTIE.

    RDS_PTIE
        use for symbolic extractor as equivalent of PTIE.

    RDS_POLY
        polysillicon run, for cell internal wirering.

    RDS_GATE
        transistor polysillicon, for gate.

    RDS_TPOLY
        polysillicon feed through. Indicate to a router that a track is free of polysillicon.

    RDS_CONT
        hole in the isolating layer between polysillicon or active area and first metal level.

    RDS_ALU1
        first metal level run.

    RDS_TALU1
        first metal level feed through. Indicates to a router that a track is free of first metal level.

    RDS_VIA1
        hole in the isolating layer between first metal level and second metal level.

    RDS_ALU2
        second metal level run.

    RDS_TALU2
        second metal level feed through. Indicate to a router that a track is free of second metal level.

    RDS_VIA2
        hole in the isolating layer between second metal level and third metal level.

    RDS_ALU3
        third metal level run.

    RDS_TALU3
        third metal level feed through. Indicate to a router that a track is free of third metal level.

    RDS_ALU4
        fourth metal. (Used only for GaAs designs.)

    RDS_VIA3
        hole in the isolating layer between third metal level and fourth metal level. (Used only for GaAs designs.)

    RDS_ACTIV
        active area dropped in N or P implant to build transistors.

    RDS_NIMP
        implant area, (sometime known as N select), for N transistors.

    RDS_PIMP
        implant area, (sometime known as P select), for P transistors.

    RDS_CPAS
        passivation, used in pads.

    RDS_USER0
        user defined purpose layer. (May be used for DRC logical operations.)

    RDS_USER1
        user defined purpose layer. (May be used for DRC logical operations.)

    RDS_USER2
        user defined purpose layer. (May be used for DRC logical operations.)

    RDS_REF
        virtual layer for the representation of symbolic references

    RDS_ABOX
        virtual layer needed to indicate the abutment box of a model.

    RDS_DEFAULT
        default layer, shall never appear anywhere.

FILE DESCRIPTION
The following lines describe the file, entry by entry, specifying what is expected.

Physical grid
    DEFINE PHYSICAL_GRID .5
    This statement defines the minimum grid spacing enforced by the foundry.

Lambda