---------------------------------------------------------------
-- description du dlxm en VHDL                               --
-- version v0.1                                              --
-- 16 novembre 1993                                          --
---------------------------------------------------------------


ENTITY dlxm IS
  PORT (
  ck    : in bit;				
  reset : in bit;				
  frz   : in bit;				
  it    : in bit_vector(3 downto 0);		
  data  : inout mux_vector(31 downto 0) bus;	
  byte  : out bit_vector(0 to 3);		
  rw    : out bit;				
  adr   : out mux_vector(31 downto 0) bus;	
  scin  : in bit;				
  test  : in bit;				
  scout : out bit;				
  vdd   : in bit;				
  vss   : in bit;				
  vddp  : in bit;				
  vssp  : in bit				
  );
END dlxm;


ARCHITECTURE structural_view OF dlxm IS
  COMPONENT core
    port (
    ad_n      : inout bit_vector(31 downto 0);	
    datain_n  : in bit_vector(31 downto 0);	
    dataout_n : out bit_vector(31 downto 0);	
    it        : in bit_vector(3 downto 0);	
    scin      : in bit;				
    scout     : out bit;			
    test      : in bit;				
    reset     : in bit;				
    frz       : in bit;				
    byte      : out bit_vector(3 downto 0);	
    rw        : out bit;			
    rw_ctl    : out bit;			
    nfrz_ctl  : out bit;			
    ck        : in bit;				
    vdd       : in bit;				
    vss       : in bit				
    );
  END COMPONENT;

  COMPONENT piot_p
    port (
    i    : in BIT;
    b    : in BIT;
    f    : out BIT;
    pad  : inout MUX_BIT bus;	
    vdde : in BIT;
    vddi : in BIT;
    vsse : in BIT;
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pot_p
    port (
    i    : in BIT;
    b    : in BIT;
    pad  : out MUX_BIT BUS;
    vdde : in BIT;
    vddi : in BIT;
    vsse : in BIT;
    vssi : in BIT
    );
  END COMPONENT;

  COMPONENT po_p
    port (
    i    : in BIT;	
    pad  : out BIT;	
    vdde : in BIT;	
    vddi : in BIT;	
    vsse : in BIT;	
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pi_p
    port (
    pad  : in BIT;	
    t    : out BIT;	
    vdde : in BIT;	
    vddi : in BIT;	
    vsse : in BIT;	
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pvddi_p
    port (
    vdd  : in BIT;	
    vdde : in BIT;	
    vddi : in BIT;	
    vsse : in BIT;	
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pvssi_p
    port (
    vss  : in BIT;	
    vdde : in BIT;	
    vddi : in BIT;	
    vsse : in BIT;	
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pvdde_p
    port (
    vdde : in BIT;	
    vsse : in BIT;	
    vssi : in BIT	
    );
  END COMPONENT;

  COMPONENT pvsse_p
    port (
    vdde : in BIT;	
    vddi : in BIT;	
    vsse : in BIT	
    );
  END COMPONENT;

  SIGNAL ck_c     : bit;
  SIGNAL frz_c    : bit;
  SIGNAL it_c     : bit_vector(3 downto 0);
  SIGNAL nadr     : bit_vector(31 downto 0);
  SIGNAL nbyte    : bit_vector(3 downto 0);	
  SIGNAL ndatain  : bit_vector(31 downto 0);	
  SIGNAL ndataout : bit_vector(31 downto 0);	
  SIGNAL nrw      : bit;	
  SIGNAL nscout   : bit;
  SIGNAL reset_c  : bit;
  SIGNAL rw_ctl   : bit;
  SIGNAL nfrz_ctl : bit;
  SIGNAL scin_c   : bit;
  SIGNAL test_c   : bit;

BEGIN

  core_dlx : core
    PORT MAP (
    vss       => vss,
    vdd       => vdd,
    ck        => ck_c,
    rw_ctl    => rw_ctl,
    nfrz_ctl  => nfrz_ctl,
    rw        => nrw,
    byte      => nbyte,
    frz       => frz_c,
    reset     => reset_c,
    test      => test_c,
    scout     => nscout,
    scin      => scin_c,
    it        => it_c,
    dataout_n => ndataout,
    datain_n  => ndatain,
    ad_n      => nadr
    );

  ad_out_pl0 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(0),
    b => nfrz_ctl,
    i => nadr(0));

  ad_out_pl1 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(1),
    b => nfrz_ctl,
    i => nadr(1));

  ad_out_pl2 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(2),
    b => nfrz_ctl,
    i => nadr(2));

  ad_out_pl3 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(3),
    b => nfrz_ctl,
    i => nadr(3));

  ad_out_pl4 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(4),
    b => nfrz_ctl,
    i => nadr(4));

  ad_out_pl5 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(5),
    b => nfrz_ctl,
    i => nadr(5));

  ad_out_pl6 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(6),
    b => nfrz_ctl,
    i => nadr(6));

  ad_out_pl7 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(7),
    b => nfrz_ctl,
    i => nadr(7));

  ad_out_pl8 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(8),
    b => nfrz_ctl,
    i => nadr(8));

  ad_out_pl9 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(9),
    b => nfrz_ctl,
    i => nadr(9));

  ad_out_pl10 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(10),
    b => nfrz_ctl,
    i => nadr(10));

  ad_out_pl11 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(11),
    b => nfrz_ctl,
    i => nadr(11));

  ad_out_pl12 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(12),
    b => nfrz_ctl,
    i => nadr(12));

  ad_out_pl13 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(13),
    b => nfrz_ctl,
    i => nadr(13));

  ad_out_pl14 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(14),
    b => nfrz_ctl,
    i => nadr(14));

  ad_out_pl15 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(15),
    b => nfrz_ctl,
    i => nadr(15));

  ad_out_pl16 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(16),
    b => nfrz_ctl,
    i => nadr(16));

  ad_out_pl17 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(17),
    b => nfrz_ctl,
    i => nadr(17));

  ad_out_pl18 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(18),
    b => nfrz_ctl,
    i => nadr(18));

  ad_out_pl19 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(19),
    b => nfrz_ctl,
    i => nadr(19));

  ad_out_pl20 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(20),
    b => nfrz_ctl,
    i => nadr(20));

  ad_out_pl21 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(21),
    b => nfrz_ctl,
    i => nadr(21));

  ad_out_pl22 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(22),
    b => nfrz_ctl,
    i => nadr(22));

  ad_out_pl23 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(23),
    b => nfrz_ctl,
    i => nadr(23));

  ad_out_pl24 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(24),
    b => nfrz_ctl,
    i => nadr(24));

  ad_out_pl25 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(25),
    b => nfrz_ctl,
    i => nadr(25));

  ad_out_pl26 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(26),
    b => nfrz_ctl,
    i => nadr(26));

  ad_out_pl27 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(27),
    b => nfrz_ctl,
    i => nadr(27));

  ad_out_pl28 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(28),
    b => nfrz_ctl,
    i => nadr(28));

  ad_out_pl29 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(29),
    b => nfrz_ctl,
    i => nadr(29));

  ad_out_pl30 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(30),
    b => nfrz_ctl,
    i => nadr(30));

  ad_out_pl31 : pot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => adr(31),
    b => nfrz_ctl,
    i => nadr(31));

  dat_inout_pl0 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(0),
    f => ndatain(0),
    b => rw_ctl,
    i => ndataout(0));

  dat_inout_pl1 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(1),
    f => ndatain(1),
    b => rw_ctl,
    i => ndataout(1));

  dat_inout_pl2 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(2),
    f => ndatain(2),
    b => rw_ctl,
    i => ndataout(2));

  dat_inout_pl3 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(3),
    f => ndatain(3),
    b => rw_ctl,
    i => ndataout(3));

  dat_inout_pl4 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(4),
    f => ndatain(4),
    b => rw_ctl,
    i => ndataout(4));

  dat_inout_pl5 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(5),
    f => ndatain(5),
    b => rw_ctl,
    i => ndataout(5));

  dat_inout_pl6 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(6),
    f => ndatain(6),
    b => rw_ctl,
    i => ndataout(6));

  dat_inout_pl7 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(7),
    f => ndatain(7),
    b => rw_ctl,
    i => ndataout(7));

  dat_inout_pl8 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(8),
    f => ndatain(8),
    b => rw_ctl,
    i => ndataout(8));

  dat_inout_pl9 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(9),
    f => ndatain(9),
    b => rw_ctl,
    i => ndataout(9));

  dat_inout_pl10 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(10),
    f => ndatain(10),
    b => rw_ctl,
    i => ndataout(10));

  dat_inout_pl11 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(11),
    f => ndatain(11),
    b => rw_ctl,
    i => ndataout(11));

  dat_inout_pl12 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(12),
    f => ndatain(12),
    b => rw_ctl,
    i => ndataout(12));

  dat_inout_pl13 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(13),
    f => ndatain(13),
    b => rw_ctl,
    i => ndataout(13));

  dat_inout_pl14 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(14),
    f => ndatain(14),
    b => rw_ctl,
    i => ndataout(14));

  dat_inout_pl15 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(15),
    f => ndatain(15),
    b => rw_ctl,
    i => ndataout(15));

  dat_inout_pl16 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(16),
    f => ndatain(16),
    b => rw_ctl,
    i => ndataout(16));

  dat_inout_pl17 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(17),
    f => ndatain(17),
    b => rw_ctl,
    i => ndataout(17));

  dat_inout_pl18 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(18),
    f => ndatain(18),
    b => rw_ctl,
    i => ndataout(18));

  dat_inout_pl19 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(19),
    f => ndatain(19),
    b => rw_ctl,
    i => ndataout(19));

  dat_inout_pl20 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(20),
    f => ndatain(20),
    b => rw_ctl,
    i => ndataout(20));

  dat_inout_pl21 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(21),
    f => ndatain(21),
    b => rw_ctl,
    i => ndataout(21));

  dat_inout_pl22 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(22),
    f => ndatain(22),
    b => rw_ctl,
    i => ndataout(22));

  dat_inout_pl23 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(23),
    f => ndatain(23),
    b => rw_ctl,
    i => ndataout(23));

  dat_inout_pl24 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(24),
    f => ndatain(24),
    b => rw_ctl,
    i => ndataout(24));

  dat_inout_pl25 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(25),
    f => ndatain(25),
    b => rw_ctl,
    i => ndataout(25));

  dat_inout_pl26 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(26),
    f => ndatain(26),
    b => rw_ctl,
    i => ndataout(26));

  dat_inout_pl27 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(27),
    f => ndatain(27),
    b => rw_ctl,
    i => ndataout(27));

  dat_inout_pl28 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(28),
    f => ndatain(28),
    b => rw_ctl,
    i => ndataout(28));

  dat_inout_pl29 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(29),
    f => ndatain(29),
    b => rw_ctl,
    i => ndataout(29));

  dat_inout_pl30 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(30),
    f => ndatain(30),
    b => rw_ctl,
    i => ndataout(30));

  dat_inout_pl31 : piot_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => data(31),
    f => ndatain(31),
    b => rw_ctl,
    i => ndataout(31));

  it_in_pl0 : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => it_c(0),
    pad => it(0));

  it_in_pl1 : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => it_c(1),
    pad => it(1));

  it_in_pl2 : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => it_c(2),
    pad => it(2));

  it_in_pl3 : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => it_c(3),
    pad => it(3));

  scin_pl : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => scin_c,
    pad => scin);

  scout_pl : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => scout,
    i => nscout);

  test_pl : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => test_c,
    pad => test);

  reset_pl : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => reset_c,
    pad => reset);

  frz_pl : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => frz_c,
    pad => frz);

  byte_pl0 : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => byte(0),
    i => nbyte(0));

  byte_pl1 : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => byte(1),
    i => nbyte(1));

  byte_pl2 : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => byte(2),
    i => nbyte(2));

  byte_pl3 : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => byte(3),
    i => nbyte(3));

  rw_pl : po_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    pad => rw,
    i => nrw);

  ck_pl : pi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    t => ck_c,
    pad => ck);

  vddi_pl_0 : pvddi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vdd => vdd);

  vddi_pl_1 : pvddi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vdd => vdd);

  vddi_pl_2 : pvddi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vdd => vdd);

  vddi_pl_3 : pvddi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vdd => vdd);

  vssi_pl_0 : pvssi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vss => vss);

  vssi_pl_1 : pvssi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vss => vss);

  vssi_pl_2 : pvssi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vss => vss);

  vssi_pl_3 : pvssi_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vddi => vddp,
    vdde => vddp,
    vss => vss);

  vdde_pl_0 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vdde_pl_1 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vdde_pl_2 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vdde_pl_3 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vdde_pl_4 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vdde_pl_5 : pvdde_p
    PORT MAP (
    vssi => vssp,
    vsse => vssp,
    vdde => vddp);

  vsse_pl_0 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_1 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_2 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_3 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_4 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_5 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

  vsse_pl_6 : pvsse_p
    PORT MAP (
    vsse => vssp,
    vddi => vddp,
    vdde => vddp);

end structural_view;
