DLX_ASM(1)

ORIGIN
This software belongs to the ALLIANCE CAD system from the
CAO-VLSI team at MASI laboratory, University P. et M. Curie
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr

NAME

DLX_ASM - assembly language for DLX processor

SYNOPSIS

dlx_asm [-p] <assembly_file> <result_vhdl_file>

DESCRIPTION

The DLX assembler, dlx_asm, takes assembly language programs, as specified bellow and produces a rom (read only memory) using a VHDL description.

The specified assembly language can be used undifferently for both CISC (micro- programmed) and RISC (pipeline) version of DLX.

For the RISC version option -p must be specified.

THE FORMAT

An assembly program is a set of statements. Each statement must be followd by a newline. An statement is of the form :

    <label> <opcode> <operands>

label is a string used to tag a specific statement or a portion of the program. A label must be followd by : (colon) if there is a newline between the label and the opcode.

opcode is a string representing either an effective instruction or a pseudo instruction.

An effective instruction is either an instruction from the DLX's instruction set or a macro-instruction. The assembler expands a macro-instruction into a set of DLX's instructions.

operands is a list of arguments. Depending on the opcode, an assmebly statement needs from 0 up to 3 arguments. Arguments must be seperated by , (comma).

A comment begins with ; (semicolon) and extends until the end of the line.

EFFECTIVE INSTRUCTIONS

Here follows the instruction set of the DLX architecture :

ADD Rd, Rs, Rt
    add register to register (signed arithmetic) :
    Rd <- Rs + Rt

ADDU Rd, Rs, Rt
    (pipeline architecture) add register to register (unsigned arithmetic) :
    Rd <- Rs + Rt

SUB Rd, Rs, Rt
    substract register from register (signed arithmetic) :
    Rd <- Rs - Rt

SUBU Rd, Rs, Rt
    (pipeline architecture) substract register from register (unsigned arithmetic) :
    Rd <- Rs - Rt

AND Rd, Rs, Rt
    perform logical and between registers :
    Rd <- Rs and Rt

OR Rd, Rs, Rt
    perform logical or between registers :
    Rd <- Rs or Rt

XOR Rd, Rs, Rt
    perform logical exclusive or between registers :
    Rd <- Rs xor Rt

ADDI Rd, Rs, I
    add immediate to register (signed arithmetic - 16 bits signed immediate extended to 32 bits) :
    Rd <- Rs + I

ADDUI Rd, Rs, I
    (pipeline architecture) add immediate to register (unsigned arithmetic - 16 bits unsigned immediate extended to 32 bits) :
    Rd <- Rs + I

SUBI Rd, Rs, I
    substract immediate from register (signed arithmetic - 16 bits signed immediate extended to 32 bits) :
    Rd <- Rs - I

SUBUI Rd, Rs, I
    (pipeline architecture) substract immediate from register (unsigned arithmetic - 16 bits unsigned immediate extended to 32 bits) :
    Rd <- Rs - I

ANDI Rd, Rs, I
    perform logical and between immediate and register (16 bits unsigned immediate extended to 32 bits) :
    Rd <- Rs and I

ORI Rd, Rs, I
    perform logical or between immediate and register (16 bits unsigned immediate extended to 32 bits) :
    Rd <- Rs or I

XORI Rd, Rs, I
    perform logical exclusive or between immediate and register (16 bits unsigned immediate extended to 32 bits) :
    Rd <- Rs xor

SLL Rd, Rs, Rt
    shift left register (only the 5 lsb of Rt are significant) :
    Rd <- Rs << Rt

SRL Rd, Rs, Rt
    shift right register (logic - only the 5 lsb of Rt are significant) :
    Rd <- Rs << Rt

SRA Rd, Rs, Rt
    shift right register (arithmetic - only the 5 lsb of Rt are significant) :
    Rd <- Rs << Rt

SLLI Rd, Rs, I
    shift left register (5 bits unsigned immediate) :
    Rd <- Rs << I

SRLI Rd, Rs, I
    shift right register (logic - 5 bits unsigned immediate) :
    Rd <- Rs << I

SRAI Rd, Rs, I
    shift right register (arithmetic - 5 bits unsigned immediate) :
    Rd <- Rs << I

LHI Rd, I
    load high order bits of register (16 bits immediate completed with 16 zeros at last significant bits) :
    Rd <- I

SEQ Rd, Rs, Rt
    set register if equal zero :
    Rd <- 1 if (Rs = Rt) else 0

SNE Rd, Rs, Rt
    set register if non equal zero :
    Rd <- 1 if (Rs != Rt) else 0

SGE Rd, Rs, Rt
    set register if greater than or equal zero :
    Rd <- 1 if (Rs >= Rt) else 0

SLE Rd, Rs, Rt
    set register if less than or equal zero :
    Rd <- 1 if (Rs <= Rt) else 0

SGT Rd, Rs, Rt
    set register if greater than :
    Rd <- 1 if (Rs > Rt) else 0

SLT Rd, Rs, Rt
    set register if less than :
    Rd <- 1 if (Rs < Rt) else 0

SEQI Rd, Rs, I
    set register if equal zero (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs = I) else 0

SNEI Rd, Rs, I
    set register if not equal zero (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs != I) else 0

SGEI Rd, Rs, I
    set register if greater than or equal zero (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs >= I) else 0

SLEI Rd, Rs, I
    set register if less than or equal zero (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs <= I) else 0

SGTI Rd, Rs, I
    set register if greater than (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs > I) else 0

SLTI Rd, Rs, I
    set register if less than (16 bits signed immediate extended to 32 bits) :
    Rd <- 1 if (Rs < I) else 0

SW Rd, Rs, I
    store register (word) into external storage (16 bits signed immediate extended to 32 bits) :
    Storage (Rs + I) <- Rd

SH Rd, Rs, I
    (pipeline architecture) store half word (2 last significant bytes) of register into external storage (16 bits signed immediate extended to 32 bits) :
    Storage (Rs + I) <- Rd

SB Rd, Rs, I
    store the last significant byte of register into external storage (16 bits signed immediate extended to 32 bits) :
    Storage (Rs + I) <- Rd

LW Rd, Rs, I
    load word into register (16 bits signed immediate extended to 32 bits) :
    Rd <- Storage (Rs + I)

LH Rd, Rs, I
    (pipeline architecture) load half word into register (16 bits signed immediate extended to 32 bits - the signed half word read from external storage is extended to 32 bits) :
    Rd <- Storage (Rs + I)

LHU Rd, Rs, I
    (pipeline architecture) load half word into register (16 bits signed immediate extended to 32 bits - the unsigned byte read from external storage is extended to 32 bits) :
    Rd <- Storage (Rs + I)

LB Rd, Rs, I
    (pipeline architecture) load a byte into register (16 bits signed immediate extended to 32 bits - the signed byte read from external storage is extended to 32 bits) :
    Rd <- Storage (Rs + I)

LBU Rd, Rs, I
    load a byte into register (16 bits signed immediate extended to 32 bits - the unsigned byte read from external storage is extended to 32 bits) :
    Rd <- Storage (Rs + I)

JR Rs
    jump register :
    PC <- Rs

JALR Rs
    jump and link register :
    PC <- Rs
    R31 <- PC + 4

MOVS2I Rd, S
    move special register (S may be IAR, SR or TVR) into integer register (privileged instruction) :
    Rd <- S

MOVI2S S, Rs
    move integer register into special register (S may be IAR, SR or TVR) (privileged instruction) :
    S <- Rs

BEQZ Rs, label
    branch if equal zero
    PC <- label if (Rs = 0)

BNEZ Rs, label
    branch if not equal zero :
    PC <- label if (Rs != 0)

J label
    jump :
    PC <- label

JAL label
    jump and link :
    PC <- label
    R31 <- PC + 4

RFE return from interrupt (privileged instruction)

TRAP I
    software interrupt (26 bits immediate : trap number)

Macro-instructions are the followings :

NOP no operation

LOADI Rd, I
    load immediate (32 bits immediate) :
    Rd <- I

PSEUDO INSTRUCTIONS

In addition to the instruction set several pseudo-instructions have been defined to enhance the readability.

EQU I
    assign the value of an immediate to a label.

ORG I
    set the address (of the first statement) of the program to the location defined by the immediate (32 bits).

START <label>
    marks the first statement of the program to be executed.

END marks the end of the program.

NOTES

A comment begins with a ; (semicolon) and extends until the end of the line.

Immediate values can be expressed using decimal, binary, octal or hexadecimal representations:

    235 decimal value

    B"01011"
        binary value

    O"376"
        octal value

    X"0f72"
        hexadecimal value

A static expression can be used instead of an immediate. The following operations are allowed inside expressions :

    +   arithmetic addition

    -   arithmetic substraction

    *   arithmetic multiplication

    >>  shift logical right

    <<  shift logical left

EXAMPLE

dlx_asm -p prog romu

SEE ALSO

vhdl(5), vbe(5), asimut(1)

SUPPORT STATUS

Please e-mail to cao-vlsi@masi.ibp.fr for bug report and suggestions.