BEH(2)

ORIGIN

Cao&Vlsi cad tools

NAME

bebus - BEH data structure

DESCRIPTION

bebus is a data structure used in BEH to represent a one-bit bused output port. A port is considered as a bused output when its value is set by at least one deconnectable driver from the inside of the circuit. For an array, each element is represented by a single structure. These are organized in the reverse order of the array's range declaration. bebus has been designed to be used in a simply chained list.

A bebus structure is composed of the following fields.

(char *) NAME
    the port's name. For an array's element, the name is the array's identifier added to the element's index seperated by a ' ' (blank space). This string is supposed been produced by namealloc()

(char) TYPE
    port's type : W (wor_bit) and, M (mux_bit)

(struct biabl *) BIABL
    list of drivers using ABLs to represent expressions

(struct binode *) BINODE
    list of drivers using BDDs to represent expressions

(struct bebus *) NEXT
    next port

SEE ALSO

abl(1), bdd(1), beh(2), biabl(2), binode(2), beh_addbebus(2), beh_delbebus(2), beh_frebebus(2), beh_rmvbebus(2), namealloc(2)

BUGS

Please e-mail to cao-vlsi@masi.ibp.fr for bug report and suggestions.