Netlist capture 
---------------
 
You are now about to capture the logical view of addaccu, commonly
known as netlist. The design methodology prevents the designer from
building the entire netlist in one shot, including pads. VLSI
design is based on hierarchy and incremental approaches.
 
The circuit netlist you have to write will be captured in two
steps:
1) capture of the core netlist.
2) capture of the chip netlist, with pads.
 
The core netlist contains standard-cells describing the logical functions
needed to design the adder, the multiplexer and the accumulator, and the
internal wires.
 
We do not use a schematic editor for netlist capture. It uses a textual
approach.

> vi addaccu.c
 
The core netlist is nothing more than a C file containing VLSI specific
function calls. Notice that the include file genlib.h
must systematically be included at the top of ALLIANCE netlist description
files.
 
The description of a netlist in C is mainly based on the DEF_LOFIG, LOCON and
LOINS functions. DEF_LOFIG defines the name of the resulting netlist view,
LOCON instanciates a new terminal in the currently opened figure, and LOINS
instanciates pre-existing cells or blocks. For more informations, please
read the on-line manual associated with each function.
 
Notice that inverters (n1_y) are used in the netlist,
while the behavioral description does not mention them. The
reason why these inverters are introduced is simple. Output pads (s0 to s3)
just invert logical signal values, so they must be inverted once more
in order to get things work.
 
Press <return> to continue.
